文件列表:

RD1006\Docs (0, 2010-08-27)
RD1006\Docs\i2cspec1.pdf (214782, 2001-03-19)
RD1006\Docs\rd1006.pdf (206891, 2010-08-27)
RD1006\Project (0, 2010-08-27)
RD1006\Project\i2c_seprom.h (0, 2010-08-25)
RD1006\Project\i2c_seprom.lci (1891, 2009-09-08)
RD1006\Project\i2c_seprom.lpf (1034, 2010-08-26)
RD1006\Project\i2c_tb_tf.udo (489, 2010-04-21)
RD1006\Project\i2c_tb_tfa.udo (513, 2009-12-04)
RD1006\Project\i2c_tb_tff.udo (529, 2010-04-21)
RD1006\Project\i2c_tb_tffa.udo (544, 2009-09-04)
RD1006\Project\i2c_tb_vhd.udo (526, 2009-12-04)
RD1006\Project\i2c_tb_vhda.udo (475, 2009-12-04)
RD1006\Project\i2c_tb_vhdaf.udo (518, 2009-09-04)
RD1006\Project\i2c_tb_vhdf.udo (505, 2009-12-02)
RD1006\Simulation (0, 2010-08-25)
RD1006\Simulation\verilog (0, 2010-08-27)
RD1006\Simulation\verilog\rtl_verilog.do (1270, 2010-08-26)
RD1006\Simulation\verilog\timing_verilog.do (1573, 2010-08-26)
RD1006\Simulation\vhdl (0, 2010-08-27)
RD1006\Simulation\vhdl\rtl_vhdl.do (1198, 2010-08-26)
RD1006\Simulation\vhdl\timing_vhdl.do (1385, 2010-08-26)
RD1006\Source (0, 2010-04-29)
RD1006\Source\verilog (0, 2010-04-29)
RD1006\Source\verilog\i2c.v (7460, 2008-11-20)
RD1006\Source\verilog\i2c_clk.v (3442, 2008-11-10)
RD1006\Source\verilog\i2c_rreg.v (3735, 2008-12-09)
RD1006\Source\verilog\i2c_st.v (9573, 2008-11-11)
RD1006\Source\verilog\i2c_wreg.v (5015, 2008-12-09)
RD1006\Source\vhdl (0, 2010-04-29)
RD1006\Source\vhdl\i2c.vhd (8979, 2009-09-03)
RD1006\Source\vhdl\i2c_clk.vhd (3358, 2009-09-03)
RD1006\Source\vhdl\i2c_rreg.vhd (3482, 2009-09-03)
RD1006\Source\vhdl\i2c_st.vhd (12166, 2009-09-03)
RD1006\Source\vhdl\i2c_wreg.vhd (4686, 2009-09-03)
RD1006\Testbench (0, 2010-04-29)
RD1006\Testbench\verilog (0, 2010-04-29)
RD1006\Testbench\verilog\clk_rst.v (4449, 2008-11-10)
RD1006\Testbench\verilog\i2c_slave.v (24709, 2009-08-12)
... ...

I2C SerialEPROM Reference Design ===================================================================================================== 1. /RD1006/Docs/rd1006.pdf --> I2C design document /RD1006/Docs/rd1006_readme.txt --> Read me file (this file) /RD1006/Docs/i2cspec1.pdf --> I2C spec 2. /RD1006/Project/i2c_seprom.h --> device header (to be modified) /RD1006/Project/i2c_seprom.lci --> preference file for ispLever Classic /RD1006/Project/i2c_seprom.lpf --> preference file for ispLever8.1SP01 or Diamond /RD1006/Project/i2c_tb_tff.udo --> script for verilog functional simulation with ispLever8.1SP01 /RD1006/Project/i2c_tb_tf.udo --> script for verilog timing simulation with ispLever8.1SP01 /RD1006/Project/i2c_tb_vhdf.udo --> script for vhdl functional simulation with ispLever8.1SP01 /RD1006/Project/i2c_tb_vhd.udo --> script for vhdl timing simulation with ispLever8.1SP01 /RD1006/Project/i2c_tb_tffa.udo --> script for verilog functional simulation with ispLever Classic /RD1006/Project/i2c_tb_tfa.udo --> script for verilog timing simulation with ispLever Classic /RD1006/Project/i2c_tb_vhdaf.udo --> script for vhdl functional simulation with ispLever Classic /RD1006/Project/i2c_tb_vhda.udo --> script for vhdl timing simulation with ispLever Classic 3. /RD1006/Simulation/verilog/rtl_verilog.do --> RTL simulation script file for verilog /RD1006/Simulation/verilog/timing_verilog.do --> Timing simulation script file for verilog /RD1006/Simulation/vhdl/rtl_vhdl.do --> RTL simulation script file for vhdl /RD1006/Simulation/vhdl/timing_vhdl.do --> Timing simulation script file for vhdl 4. /RD1006/Source/verilog/i2c.v --> verilog source file - top level /RD1006/Source/verilog/i2c_clk.v --> verilog source file /RD1006/Source/verilog/i2c_rreg.v --> verilog source file /RD1006/Source/verilog/i2c_wreg.v --> verilog source file /RD1006/Source/verilog/i2c_st.v --> verilog source file /RD1006/Source/vhdl/i2c.vhd --> vhdl source file - top level /RD1006/Source/vhdl/i2c_clk.vhd --> vhdl source file /RD1006/Source/vhdl/i2c_rreg.vhd --> vhdl source file /RD1006/Source/vhdl/i2c_wreg.vhd --> vhdl source file /RD1006/Source/vhdl/i2c_st.vhd --> vhdl source file 5. /RD1006/testbench/verilog/i2c_tb.v --> Testbench for verilog simulation - top-level /RD1006/testbench/verilog/micro.v --> Testbench for verilog simulation /RD1006/testbench/verilog/i2c_slave.v --> Testbench for verilog simulation /RD1006/testbench/verilog/clk_rst.v --> Testbench for verilog simulation /RD1006/testbench/vhdl/i2c_tb.vhd --> Testbench for vhdl simulation - top-level ============================================================================================================= Important notes: 1. Unzip the RD1006_revyy.y.zip file using the existing folder names. 2. If there is a lpf file or lci file available for the reference design, copy the contents of the provided lpf file to the .lpf file under your newly created XO or FPGA project, or the contents of the provided lct file to the .lct under your cpld project. 3. If there is sty file (strategy file for Diamond) available for the design, go to File List tab on the left side of the GUI. Right click on Strategies >> Add >> Existing File. Then right click on the imported file name and select "Set as Active Strategy". 4. The .do simulation scripts are location specific. User must modify the paths to point to their library location or Diamond project paths. 5. The .udo simulation scripts are for ispLEVER8.1 SP01 and ispLEVER Classic simulation. If user selects the verilog source and ispLEVER8.1 SP01 for his project,he needs to copy 2 files(i2c_tb_tff.udo,i2c_tb_tf.udo )to the project directory where *.syn resides. If user selects the vhdl source and ispLEVER8.1 SP01 for his project, he needs to copy 2 files(i2c_tb_vhdf.udo,i2c_tb_vhd.udo) to the project directory where *.syn resides. If user selects the verilog source and ispLEVER classic for his project,he needs to copy 2 files(i2c_tb_tffa.udo,i2c_tb_tfa.udo )to the project directory where *.syn resides. If user selects the vhdl source and ispLEVER classic for his project, he needs to copy 2 files(i2c_tb_vhdaf.udo ,i2c_tb_vhda.udo)to the project directory where *.syn resides. =============================================================================================================== How to create a ispLEVER or ispLEVER Classic project: 1. Create a new ispLEVER or ispLever Classic project; 2. Use rd1006.pdf to see which device /speedgrade should be selected to achieve the desired timing result; 3. Make sure provided lpf or lct is used in the current directory. How to run simulation from ispLEVER or ispLEVER Classic project: 1. In the Project Navigator, highlight the testbench\\i2c_tb.v(vhd) file on the left-side panel,user will see 3 simulation options on the right panel 2. For functional simulation, double click on verilog or vhdl Functional Simulation with Aldec Active-HDL. Aldec simulator will be brought up, click yes to overwrite the existing file 3. Functional simulation will run until complete. user will see a script shown in the Console panel like this: i2c_tb.SEP Using 7 Bit Addressing 510: Coming out of Reset 510: Writing Word Address 540: Simulation Starting 103095 i2c_tb.SEP << 7 bit addressing & address is 10100000 >> 185025 i2c_tb.SEP << Slave Data Received on write is 01010101 >> 307905 i2c_tb.SEP << 7 bit addressing & address is 10100001 >> 394935 i2c_tb.SEP << Slave Data transmitted on read is 01010101 >> 394935 i2c_tb.SEP No ACK on a Data Read, returning to Idle 412270 leaving monitor 413270: Reading Data 413310: Data = 55 423310: Writing Word Address 525855 i2c_tb.SEP << 7 bit addressing & address is 10100000 >> 607785 i2c_tb.SEP << Slave Data Received on write is 10101010 >> 730665 i2c_tb.SEP << 7 bit addressing & address is 10100001 >> 817695 i2c_tb.SEP << Slave Data transmitted on read is 10101010 >> 817695 i2c_tb.SEP No ACK on a Data Read, returning to Idle 835030 leaving monitor 836030: Reading Data 836070: Data = aa 836070 << Simulation complete with 0 errors >> # RUNTIME: RUNTIME_0070 micro.v (150): $stop called. 4. For timing simulation, double click on verilog or vhdl Post-Route Timing Simulation with Aldec Active-HDL. Similar message will be shown in the console panel of the Aldec Active-HDL simulator. ==================================================================================================================================== How to create a project in Diamond: 1. Unzip the RD1006_revyy.y.zip file using the existing folder names, where yy.y is the current version of the zip file. 2. Bring up Diamond software, in the GUI, select File >> New Project, click Next. 3. In the New Project popup, select the Project location and provide a Project name, click Next. Note: default project location is \RD1006\project\_diamond\. default project name is i2c_seprom. 4. Add the necessary source files from the RD1006\source directory, click Next. 5. Select device, speedgrade,package, click Next. 6. Click Finish. Now the project is successfully created. 7. If there is lpf file available for the reference design, go to File List tab on the left side of the GUI. Right click on constraint File >> Add >> Existing File. Then right click on the imported file name and select "Set as Active Preference file". 8. If there is sty file available for the reference design, go to File List tab on the left side of the GUI. Right click on Strategies >> Add >> Existing File. Then right click on the imported file name and select "Set as Active Strategy". How to run simulation under Diamond: 1. Go to \RD1006\simulation directory, open rtl_.do or timing_.do to modify the paths to point to current directory. 1.1 create the directory location for your simulation, \RDxxxx\simulation\\rtl or \RDxxxx\simulation\\timing are default locations. 2. Bring up Active-HDL from Diamond environment. Click cancel when pop up windows come up. 3. For functional simulation, go to Tools >> Execute Macros, browse to \RD1006\simulation\\rtl directory, select rtl_.do. This should run simulation all the way to the end. Error in this stage is often caused by incorrect paths for source / testbench, etc. 4. For timing simulation, go to Tools >> Execute Macros, browse to \RD1006\simulation\post_route directory, select timing_.do. Make sure the post-route netlist file is available in the correct location. This should run simulation all the way to the end. Error in this stage is often caused by incorrect paths for source / testbench, etc. ============================================================================================================================================================================== How to run Fit/Place and Route, JEDEC generation, and Timing Analysis in ispLEVER: 1. Highlight the device on the left-side panel of the Project Navigator (ispLEVER). On the right-side panel, a. if it is 4000ZE device, double click on Fit Design. This will bring the deisgn through fitting. b. if it is XO/XO2/XP2 device, double click on Place and Route Design. This will bring the design through synthesis, mapping, and place and route. 2. Highlight the device on the left-side panel of the Project Navigator. On the right-side panel, double click on. a. JEDEC file for 4000ZE design flow. b. Generate Data File (JEDEC) for XO or FPGA deisgn flow. This will generate the jedec file for the design. 3. For timing information, double click on a. Timing Analysis for 4000ZE deisgn, b. Place and Route Trace Report for XO or FPGA design to get the timing analysis result. How to run Place and Route, JEDEC generation, and Timing Analysis in Diamond: 1. Double click the process in the Process panel to run the process, e.g. double click on Place and Route design. 2. Double click on Export File >> JEDEC file to generate the jedec files. 3. Run the Place and Route Trace, then go to Report tab to view the TRACE report.

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