51
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：741KB
下载次数：7
上传日期：2012-12-06 10:53:06
上 传 者：
lvpw
说明： 完整的8051的IP核，用VHDL语言描述,对于从事SoC设计和相关IC设计的人员有帮助
(the ip core of c8051,described in VHDL language)
文件列表:
51 (0, 2008-08-27)
51\doc (0, 2012-12-06)
51\doc\c8051.pdf (17358, 2001-02-15)
51\doc\c8051_a.pdf (160250, 2001-10-04)
51\doc\c8051_b.pdf (63831, 2001-10-04)
51\doc\c8051_dsn.pdf (59198, 2001-10-04)
51\doc\c8051_spec.pdf (450977, 2001-10-04)
51\src (0, 2008-08-27)
51\src\core (0, 2012-12-06)
51\src\core\alu.vhd (82191, 2001-10-02)
51\src\core\c8051.vhd (50058, 2001-10-02)
51\src\core\c8051_cfg.vhd (4878, 2001-10-02)
51\src\core\clkctrl.vhd (6765, 2001-10-03)
51\src\core\cpu.vhd (55418, 2001-10-02)
51\src\core\isr.vhd (20508, 2001-10-02)
51\src\core\memctrl.vhd (60335, 2001-10-02)
51\src\core\oci.vhd (10332, 2001-10-02)
51\src\core\ports.vhd (10613, 2001-10-02)
51\src\core\ramsfrctrl.vhd (60378, 2001-10-02)
51\src\core\serial.vhd (47091, 2001-10-02)
51\src\core\timer.vhd (36438, 2001-10-02)
51\src\core\utility.vhd (28651, 2001-10-02)
51\src\tb (0, 2012-12-06)
51\src\tb\chip (0, 2012-12-06)
51\src\tb\chip\chip8051.vhd (23374, 2001-10-01)
51\src\tb\chip\chipoci.vhd (3254, 2001-10-02)
51\src\tb\chip\chippad.vhd (2641, 2001-10-01)
51\src\tb\chip\chipram.vhd (3836, 2001-10-01)
51\src\tb\chip\chiprom.vhd (9547, 2001-10-01)
51\src\tb\chip\chipsfr.vhd (3843, 2001-10-01)
51\src\tb\env (0, 2012-12-06)
51\src\tb\env\extacs.vhd (12991, 2001-10-01)
51\src\tb\env\extclock.vhd (4471, 2001-10-01)
51\src\tb\env\extcomp.vhd (16306, 2001-10-01)
51\src\tb\env\extlatch.vhd (2199, 2001-10-01)
51\src\tb\env\extram.vhd (3849, 2001-10-01)
51\src\tb\env\extrom.vhd (9587, 2001-10-01)
51\src\tb\env\extshift.vhd (3685, 2001-10-01)
51\src\tb\env\extstim.vhd (6335, 2001-10-01)
51\src\tb\tb.vhd (29502, 2001-10-03)
... ...
Please follow the steps to execute macros for Aldec
in ActiveVHDL simulator:
1. Work directory which contain directories source code files \SRC
should have C8051 name. If you want to rename this directory you have to
change variable directory in CRE_COMP.DO file, for example like this:
set directory user_project_name
2. Change path to variable DIR in file CRE_COMP.DO to directory which contain
C8051 directory for example:
set DIR C:\DESIGNS
3. Start Active-VHDL without loading project.
4. Execute CRE_COMP.DO macro to create and compile project.
5. Run either ADD_WAVE.DO macro to start simulation with default project
settings or
6. Run OP_TESTS.DO macro to simulate set of tests series OP_TESTS or
7. Run EX_TESTS.DO macro to simulate set of tests series EX_TESTS or
8. Run PE_TESTS.DO macro to simulate set of tests series PE_TESTS.
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