文件列表:

spi_master_slave (0, 2011-09-20)
spi_master_slave\branches (0, 2011-09-20)
spi_master_slave\tags (0, 2011-09-20)
spi_master_slave\trunk (0, 2011-09-20)
spi_master_slave\trunk\doc (0, 2011-09-20)
spi_master_slave\trunk\doc\src (0, 2012-11-06)
spi_master_slave\trunk\doc\src\spi_master_slave_Specifications.doc (262144, 2011-08-09)
spi_master_slave\trunk\doc\src\SPI_MODES.jpg (42808, 2011-05-30)
spi_master_slave\trunk\doc\src\Thumbs.db (5120, 2012-11-06)
spi_master_slave\trunk\doc\UNDER_CONSTRUCTION.txt (225, 2011-07-13)
spi_master_slave\trunk\license (0, 2011-09-20)
spi_master_slave\trunk\license\lgpl.txt (7651, 2011-08-30)
spi_master_slave\trunk\rtl (0, 2011-09-20)
spi_master_slave\trunk\rtl\spi_master_slave (0, 2011-09-20)
spi_master_slave\trunk\rtl\spi_master_slave\grp_debouncer.vhd (13211, 2011-09-20)
spi_master_slave\trunk\rtl\spi_master_slave\spi_loopback.ucf (3969, 2011-09-20)
spi_master_slave\trunk\rtl\spi_master_slave\spi_loopback.vhd (6078, 2011-09-20)
spi_master_slave\trunk\rtl\spi_master_slave\spi_loopback_test.vhd (14081, 2011-09-20)
spi_master_slave\trunk\rtl\spi_master_slave\spi_master.vhd (43690, 2011-09-20)
spi_master_slave\trunk\rtl\spi_master_slave\spi_slave.vhd (34143, 2011-09-20)
spi_master_slave\trunk\syn (0, 2011-09-20)
spi_master_slave\trunk\syn\ATLYS_01.SET (28058, 2011-07-11)
spi_master_slave\trunk\syn\ATLYS_02.SET (28082, 2011-07-17)
spi_master_slave\trunk\syn\ATLYS_03.SET (21308, 2011-07-29)
spi_master_slave\trunk\syn\ATLYS_04.SET (21306, 2011-08-02)
spi_master_slave\trunk\syn\ATLYS_05.SET (21327, 2011-08-29)
spi_master_slave\trunk\syn\fuse.xmsgs (367, 2011-08-11)
spi_master_slave\trunk\syn\fuseRelaunch.cmd (291, 2011-09-20)
spi_master_slave\trunk\syn\grp_debouncer.vhd (13211, 2011-09-20)
spi_master_slave\trunk\syn\par_usage_statistics.html (4139, 2011-09-20)
spi_master_slave\trunk\syn\sim_master_slave_ct.pdf (173295, 2011-08-11)
spi_master_slave\trunk\syn\spi_master.vhd (43690, 2011-08-30)
spi_master_slave\trunk\syn\spi_master_atlys.ucf (21710, 2011-09-20)
spi_master_slave\trunk\syn\spi_master_atlys_test.vhd (6935, 2011-09-20)
spi_master_slave\trunk\syn\spi_master_atlys_top.drc (211, 2011-08-29)
spi_master_slave\trunk\syn\spi_master_atlys_top.par (9094, 2011-09-20)
spi_master_slave\trunk\syn\spi_master_atlys_top.pcf (2383, 2011-09-20)
spi_master_slave\trunk\syn\spi_master_atlys_top.syr (49366, 2011-09-20)
... ...

SPI_MASTER_ATLYS ================ This is a ISE 13.1 project to test the spi_master.vhd, spi_slave.vhd and grp_debouncer.vhd models in silicon. The target board is a Digilent Atlys FPGA board (Spartan-6 @ 100MHz), and the circuit was tested at different SPI clock frequencies. See the scope screenshots in the spi_master_scope_photos.zip file for each SPI frequency tested. The circuit verifies both master and slave cores, with transmit and receive streams operating full-duplex at 50MHz of SPI clock. This circuit also includes a very robust debouncing circuit to use with multiple inputs. The model, "grp_debouncer.vhd" is also published under a LGPL license. The files are: ------------- spi_master.vhd vhdl model for the spi_master interface spi_slave.vhd vhdl model for the spi_slave interface grp_debouncer.vhd vhdl model for the switch debouncer spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys board spi_master_atlys_test.vhd testbench for the synthesizable toplevel 'spi_master_atlys_top.vhd' spi_master_atlys.xise ISE 13.1 project file spi_master_atlys.ucf pin lock constraints for the Atlys board spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests spi_master_envsettings.html synthesis env settings, with the tools setup used ATLYS_0x.SET Tek MSO2014 settings files with the debug pin names spi_master_atlys_top_bit.zip bitgen file to program the Atlys board LICENSING --------- This work is licensed as a LGPL work. If you find this licensing too restrictive for hardware, or it is not adequate for you, please get in touch with me and we can arrange a more suitable open source hardware licensing. If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer, or send me e-mail: jdoin@opencores.org If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at http://opencores.org/project,spi_master_slave,bugtracker If you find this core useful, please let me know: jdoin@opencores.org In any case, thank you very much for testing this core. Jonny Doin jdoin@opencores.org

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