文件列表:

vhdl_lab (0, 2000-05-09)
vhdl_lab\hdl (0, 2000-05-09)
vhdl_lab\hdl\datapath_entity.vhd (779, 1998-10-01)
vhdl_lab\hdl\datapath_datapathRtl.vhd (2055, 1998-10-01)
vhdl_lab\hdl\control_entity.vhd (658, 1998-10-01)
vhdl_lab\hdl\control_fsm.vhd (2642, 1998-10-01)
vhdl_lab\hdl\tollBoothTop_entity.vhd (671, 1998-10-01)
vhdl_lab\hdl\tollBoothTop_struct.vhd (2515, 2000-05-09)
vhdl_lab\hdl\tester_entity.vhd (656, 1998-10-01)
vhdl_lab\hdl\TollBoothTestbench_entity.vhd (322, 1998-10-01)
vhdl_lab\hdl\TollBoothTestbench_struct.vhd (2322, 2000-05-09)
vhdl_lab\hdl\tester_testerArch.vhd (1668, 1998-10-01)
vhdl_lab\compile (333, 2000-05-09)

1) set up UNIX environment for Mentor (see C61 web page/newsgroup) or see C03, etc (I tested this on my work environment, which has a different setup) 2) in this directory, type: vlib work 3) run the compile script (which runs vcom) 4) type: vsim 5) in vsim, select the testbench to load 6) add the top level signals to the wave window 7) type "run 1000" in the simulator command window 8) if the fares are correct, you are ready to complete the lab

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