UART_Universal
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：19KB
下载次数：3
上传日期：2012-12-28 13:48:19
上 传 者：
wangwh900
说明： 基于FPGA逻辑单元设计的通用异步串行接口设计UART，波特率参数化，模块分解易懂易上手
(General UART Design based on FPGA logic)
文件列表:
CLK_MANAGE.vhd (1776, 2009-08-17)
CLKDIV16.vhd (726, 2009-08-17)
CLKDIV27.vhd (1213, 2009-08-17)
Count_16x.vhd (887, 2009-08-17)
counter.vhd (819, 2009-08-17)
counter_S.vhd (835, 2009-08-17)
detector.vhd (1656, 2009-08-17)
detector_tb.vhd (3967, 2009-08-17)
parity_verifier.vhd (638, 2009-08-17)
sample16x.vhd (1044, 2009-08-17)
shift_register.vhd (1011, 2009-08-17)
State.vhd (1337, 2009-08-17)
switch.vhd (429, 2009-08-17)
switch_bus.vhd (696, 2009-08-17)
UART.vhd (9230, 2009-08-17)
uart_core.vhd (7062, 2009-08-17)
UART_DLL.vhd (2817, 2009-08-17)
UART_DLL_tb.vhd (4414, 2009-08-17)
UART_PACKAGE.vhd (5080, 2009-08-17)
uart_top_tb.vhd (5290, 2009-08-17)
baudrate_generator.vhd (1365, 2009-08-17)
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