文件列表:

lab2_Freq_20120510 (0, 2012-12-14)
lab2_Freq_20120510\Freq (0, 2012-12-14)
lab2_Freq_20120510\Freq\1.wcfg (13418, 2011-06-28)
lab2_Freq_20120510\Freq\2.wcfg (15308, 2012-05-10)
lab2_Freq_20120510\Freq\Freq.gise (6322, 2012-12-14)
lab2_Freq_20120510\Freq\Freq.xise (35189, 2012-12-14)
lab2_Freq_20120510\Freq\Freq_ise12migration.zip (2600461, 2011-11-23)
lab2_Freq_20120510\Freq\_xmsgs (0, 2012-12-14)
lab2_Freq_20120510\Freq\_xmsgs\netgen.xmsgs (665, 2012-12-14)
lab2_Freq_20120510\Freq\_xmsgs\xst.xmsgs (4422, 2012-12-14)
lab2_Freq_20120510\Freq\data_process1.cmd_log (248, 2011-06-27)
lab2_Freq_20120510\Freq\data_process1.v (1923, 2011-06-28)
lab2_Freq_20120510\Freq\data_process2.cmd_log (248, 2011-06-27)
lab2_Freq_20120510\Freq\data_process2.v (1623, 2011-06-27)
lab2_Freq_20120510\Freq\freq.cmd_log (221, 2011-06-27)
lab2_Freq_20120510\Freq\freq.v (3319, 2007-08-24)
lab2_Freq_20120510\Freq\fuse.xmsgs (809, 2007-08-24)
lab2_Freq_20120510\Freq\fuseRelaunch.cmd (239, 2007-08-24)
lab2_Freq_20120510\Freq\ipcore_dir (0, 2012-12-14)
lab2_Freq_20120510\Freq\ipcore_dir\.lso (14, 2011-06-23)
lab2_Freq_20120510\Freq\ipcore_dir\_xmsgs (0, 2012-12-14)
lab2_Freq_20120510\Freq\ipcore_dir\_xmsgs\cg.xmsgs (676, 2012-12-14)
lab2_Freq_20120510\Freq\ipcore_dir\_xmsgs\pn_parser.xmsgs (785, 2007-08-24)
lab2_Freq_20120510\Freq\ipcore_dir\coregen.cgc (21219, 2012-12-14)
lab2_Freq_20120510\Freq\ipcore_dir\coregen.cgp (238, 2012-12-14)
lab2_Freq_20120510\Freq\ipcore_dir\coregen.log (323, 2012-12-14)
lab2_Freq_20120510\Freq\ipcore_dir\create_freq_chufaqi_2.tcl (1275, 2011-06-23)
lab2_Freq_20120510\Freq\ipcore_dir\create_gen_dds.tcl (1268, 2011-06-24)
lab2_Freq_20120510\Freq\ipcore_dir\create_gen_dds1.tcl (1269, 2011-06-28)
lab2_Freq_20120510\Freq\ipcore_dir\edit_freq_chufaqi_2.tcl (1129, 2007-08-24)
lab2_Freq_20120510\Freq\ipcore_dir\edit_gen_dds.tcl (1122, 2012-12-14)
lab2_Freq_20120510\Freq\ipcore_dir\freq_chufaqi_2.asy (641, 2011-06-23)
lab2_Freq_20120510\Freq\ipcore_dir\freq_chufaqi_2.gise (2495, 2012-05-23)
lab2_Freq_20120510\Freq\ipcore_dir\freq_chufaqi_2.ncf (0, 2012-05-10)
lab2_Freq_20120510\Freq\ipcore_dir\freq_chufaqi_2.ngc (60292, 2011-06-23)
lab2_Freq_20120510\Freq\ipcore_dir\freq_chufaqi_2.sym (1845, 2011-06-23)
lab2_Freq_20120510\Freq\ipcore_dir\freq_chufaqi_2.v (81530, 2011-06-23)
lab2_Freq_20120510\Freq\ipcore_dir\freq_chufaqi_2.veo (4752, 2011-06-23)
lab2_Freq_20120510\Freq\ipcore_dir\freq_chufaqi_2.vhd (98736, 2011-06-23)
lab2_Freq_20120510\Freq\ipcore_dir\freq_chufaqi_2.vho (5072, 2011-06-23)
... ...

The following files were generated for 'gen_dds' in directory G:\Training_Labs\lab2_Freq_20120510\Freq\ipcore_dir\ Generate XCO file: CORE Generator input file containing the parameters used to generate a core. * gen_dds.xco Generate Implementation Netlist: Binary Xilinx implementation netlist files containing the information required to implement the module in a Xilinx (R) FPGA. * gen_dds.ngc Obfuscate Netlist Generator: Please see the core data sheet. * gen_dds.ngc Generate Instantiation Templates: Template files containing code that can be used as a model for instantiating a CORE Generator module in an HDL design. * gen_dds.veo RTL Simulation Model Generator: Please see the core data sheet. * gen_dds.v All Documents Generator: Please see the core data sheet. * gen_dds/doc/dds_compiler_v4_0_vinfo.html * gen_dds/doc/dds_ds558.pdf Deliver IP Symbol: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. * gen_dds.asy SYM file generator: Generate a SYM file for compatibility with legacy flows * gen_dds.sym Generate XMDF file: ISE Project Navigator interface file. ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project. * gen_dds_xmdf.tcl Generate ISE project file: ISE Project Navigator support files. These are generated files and should not be edited directly. * _xmsgs/pn_parser.xmsgs * gen_dds.gise * gen_dds.xise Deliver Readme: Readme file for the IP. * gen_dds_readme.txt Generate FLIST file: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. * gen_dds_flist.txt Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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