文件列表:

fpga fir\coregen_xil_2600_47.cgc (2073, 2011-09-30)
fpga fir\coregen_xil_2600_47.cgp (518, 2011-09-30)
fpga fir\fir_core.mif (342, 2011-09-30)
fpga fir\fir_coreCOEFF_auto0_0.mif (36, 2011-09-30)
fpga fir\fir_coreCOEFF_auto0_1.mif (36, 2011-09-30)
fpga fir\fir_coreCOEFF_auto0_2.mif (36, 2011-09-30)
fpga fir\fir_coreCOEFF_auto0_3.mif (36, 2011-09-30)
fpga fir\fir_coreCOEFF_auto0_4.mif (36, 2011-09-30)
fpga fir\fir_coreCOEFF_auto0_5.mif (36, 2011-09-30)
fpga fir\fir_coreCOEFF_auto0_6.mif (36, 2011-09-30)
fpga fir\fir_coreCOEFF_auto0_7.mif (36, 2011-09-30)
fpga fir\fir_coreCOEFF_auto0_8.mif (36, 2011-09-30)
fpga fir\fir_coreCOEFF_auto0_9.mif (36, 2011-09-30)
fpga fir\fir_corefilt_decode_rom.mif (51, 2011-09-30)
fpga fir\fir_data.coe (305, 2011-09-30)
fpga fir\fir_demo.gise (5887, 2012-05-06)
fpga fir\fir_demo.xise (36455, 2012-05-06)
fpga fir\fir_top.v (774, 2012-05-06)
fpga fir\fir_top_summary.html (3706, 2012-05-06)
fpga fir\fuse.log (1864, 2012-05-06)
fpga fir\fuse.xmsgs (572, 2012-05-06)
fpga fir\fuseRelaunch.cmd (274, 2012-05-06)
fpga fir\ipcore_dir\.lso (19, 2012-05-06)
fpga fir\ipcore_dir\coregen.log (2995, 2012-05-06)
fpga fir\ipcore_dir\edit_fir_core.tcl (1123, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0.asy (545, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0.gise (1400, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0.mif (342, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0.ngc (296239, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0.sym (1553, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0.v (364855, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0.veo (4730, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0.xco (3002, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0.xise (40552, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0COEFF_auto0_0.mif (54, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0COEFF_auto0_1.mif (54, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0COEFF_auto0_2.mif (54, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0COEFF_auto0_3.mif (54, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0COEFF_auto0_4.mif (54, 2012-05-06)
fpga fir\ipcore_dir\fir_compiler_v5_0filt_decode_rom.mif (51, 2012-05-06)
... ...

The following files were generated for 'fir_core' in directory E:\PX\LZ\L1\LAB4\fir_demo\ipcore_dir\ fir_core.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. fir_core.gise: ISE Project Navigator support file. This is a generated file and should not be edited directly. fir_core.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_core.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. fir_core.sym: Please see the core data sheet. fir_core.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. fir_core.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. fir_core.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. fir_core.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. fir_core.xco: CORE Generator input file containing the parameters used to regenerate a core. fir_core.xise: ISE Project Navigator support file. This is a generated file and should not be edited directly. fir_coreCOEFF_auto0_0.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_coreCOEFF_auto0_1.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_coreCOEFF_auto0_2.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_coreCOEFF_auto0_3.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_coreCOEFF_auto0_4.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_coreCOEFF_auto0_5.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_coreCOEFF_auto0_6.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_coreCOEFF_auto0_7.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_coreCOEFF_auto0_8.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_coreCOEFF_auto0_9.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_core_readme.txt: Text file indicating the files generated and how they are used. fir_core_xmdf.tcl: ISE Project Navigator interface file. ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project. fir_corefilt_decode_rom.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fir_core_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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