sata_controller_core_latest

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:474KB
下载次数:61
上传日期:2013-03-24 01:36:20
上 传 者07111971
说明:  sata_controller in verilog

文件列表:
sata_controller_core_latest (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\branches (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\tags (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\blockdiagram (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\ChipScope (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\ChipScope\project.cpj (1248849, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\data (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\data\system.ucf (9750, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\etc (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\etc\bitgen.ut (66, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\etc\download.cmd (109, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\etc\fast_runtime.opt (2794, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\init_bram.sh (399, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\coregen (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\coregen\.lso (20, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\coregen\coregen.cgp (517, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\coregen\Makefile (535, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\coregen\npi_if_ila.xco (3918, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\coregen\npi_if_tx_ila.xco (3915, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\coregen\npi_ila.xco (3914, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\coregen\rx_fifo.xco (2492, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\coregen\tx_fifo.xco (2494, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\data (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\data\npi_core_v2_1_0.bbd (79, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\data\npi_core_v2_1_0.mpd (3356, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\data\npi_core_v2_1_0.pao (496, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\devl (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\devl\create.cip (3035, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\devl\ipwiz.log (5706, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\devl\ipwiz.opt (153, 2012-06-13)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\hdl (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\hdl\vhdl (0, 2013-01-12)
sata_controller_core_latest\sata_controller_core\trunk\sata2_bus_v1_00_a\base_system\pcores\npi_core_v1_00_a\hdl\vhdl\npi.vhd (44828, 2012-06-13)
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This Xilinx Base System (created with 12.2) includes the SATA2 Core with interfaces to PLB for command, control and status and to DDR through NPI for data. A C test program which runs on Microblaze to exercise the core is under "sata_test". Note: Use Makefiles under the respective coregen directories of the SATA and NPI cores to generate netlists for FIFOs and ILAs. Then copy or link these to the netlist directories.

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