xitong
所属分类:VHDL/FPGA/Verilog
开发工具:matlab
文件大小:858KB
下载次数:6
上传日期:2013-03-26 16:33:23
上 传 者:
gao_rr
说明: 包括ask信号的发送接收全过程,包括调制解调,多节传输,频域时域的分析
(Ask the signal transmission and reception of the entire process, including modulation and demodulation, the multi-cell transmission, the frequency domain to the time domain analysis)
文件列表:
xitong\Matlabcasestudy-Beng(ASK有代码).pdf (79302, 2009-05-22)
xitong\ask under noise.fig (349992, 2013-03-26)
xitong\ask wave time and frequency domain.fig (211981, 2013-03-26)
xitong\systerm.m (5117, 2009-05-27)
xitong\多径接收.fig (245155, 2013-03-26)
xitong (0, 2009-05-27)
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