Timing
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：149KB
下载次数：10
上传日期：2013-03-28 16:50:21
上 传 者：
xingfumxx
说明： 此为时域均衡的程序，主要用于OFDM接收系统，用verilog编写，很好
(This time domain equalization program, mainly for OFDM receiving system, written in verilog good)
文件列表:
Timing\Correlating_and_Accumulating.v (12134, 2008-07-10)
Timing\Magnitude_Simplified_Computing.v (2763, 2008-07-10)
Timing\Match_Filtering.v (1282, 2008-07-10)
Timing\Peak_Finding.v (1449, 2008-07-10)
Timing\Quantization.v (3128, 2008-07-10)
Timing\Simple_Correlation.v (3086, 2008-07-10)
Timing\Symbol_Output.v (4443, 2008-07-10)
Timing\Time_Syncronization.v (1647, 2008-07-10)
Timing\Time_Syncronization_summary.html (2344, 2008-07-10)
Timing\Timing_Symcronization.ise (239161, 2008-07-10)
Timing\Timing_Symcronization.ise_ISE_Backup (239161, 2008-07-10)
Timing\Timing_Symcronization.restore (48970, 2008-07-10)
Timing\__ISE_repository_Timing_Symcronization.ise_.lock (200, 2008-07-10)
Timing\_xmsgs (0, 2008-07-10)
Timing (0, 2008-07-10)
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