CooperativeCommunication
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：10305KB
下载次数：13
上传日期：2013-03-28 17:01:24
上 传 者：
xingfumxx
说明： 1. 研究空时分组码的编译码原理及算法；
2. 研究了几种不同的协作分集系统模型和协作分集协议；
3. 将空时分组码编译码器与协同通信用硬件描述语言Verilog实现，并在ISE集成环境中综合仿真，结果正确后下载到FPGA电路板上；
4. 用示波器观察输出数据是否正确，验证空时分组码协同通信的性能。
(1. Decoding Principles of space-time block codes and algorithms 2. Study several different system model of cooperative diversity and cooperative diversity protocol 3 space-time block code codec and collaborative communication using the Verilog hardware description language to achieve ISE Integrated environment and comprehensive simulation results correctly downloaded to the FPGA circuit board observed with an oscilloscope output data is correct, verify empty block codes collaborative communication performance.)
文件列表:
CooperativeCommunication\.lso (6, 2013-04-26)
CooperativeCommunication\addtou1.v (1882, 2013-04-26)
CooperativeCommunication\addtou2.v (1794, 2013-04-26)
CooperativeCommunication\chouqu1.v (1342, 2013-04-26)
CooperativeCommunication\chouqu2.v (1341, 2013-04-26)
CooperativeCommunication\chouqu3.v (1225, 2013-04-26)
CooperativeCommunication\compxlib.cfg (7091, 2013-04-26)
CooperativeCommunication\compxlib.log (86954, 2013-04-26)
CooperativeCommunication\CooperativeCommunication.ise (410258, 2013-06-29)
CooperativeCommunication\CooperativeCommunication.ise_ISE_Backup (410258, 2013-06-29)
CooperativeCommunication\CooperativeCommunication.ntrc_log (116, 2013-04-26)
CooperativeCommunication\CooperativeCommunication.restore (51939, 2013-06-29)
CooperativeCommunication\fenpin0.v (876, 2013-04-26)
CooperativeCommunication\fenpin1.v (891, 2013-04-26)
CooperativeCommunication\fircoe100K.coe (166, 2013-04-26)
CooperativeCommunication\geng1.v (821, 2013-04-26)
CooperativeCommunication\geng2.v (818, 2013-04-26)
CooperativeCommunication\hebing.v (1382, 2013-04-26)
CooperativeCommunication\jiance1.v (872, 2013-04-26)
CooperativeCommunication\jiance2.v (872, 2013-04-26)
CooperativeCommunication\jiema.v (1670, 2013-04-26)
CooperativeCommunication\jieshou.v (844, 2013-04-26)
CooperativeCommunication\jizhan.v (1956, 2013-04-26)
CooperativeCommunication\lvbo1.v (1329, 2013-04-26)
CooperativeCommunication\lvbo2.v (1329, 2013-04-26)
CooperativeCommunication\lvbo3.v (1884, 2013-04-26)
CooperativeCommunication\lvboqi.asy (694, 2013-04-26)
CooperativeCommunication\lvboqi.mif (120, 2013-04-26)
CooperativeCommunication\lvboqi.ngc (289601, 2013-04-26)
CooperativeCommunication\lvboqi.sym (1105, 2013-04-26)
CooperativeCommunication\lvboqi.v (364643, 2013-04-26)
CooperativeCommunication\lvboqi.veo (3045, 2013-04-26)
CooperativeCommunication\lvboqi.vhd (350329, 2013-04-26)
CooperativeCommunication\lvboqi.vho (3553, 2013-04-26)
CooperativeCommunication\lvboqi.xco (1705, 2013-04-26)
CooperativeCommunication\lvboqi_flist.txt (178, 2013-04-26)
CooperativeCommunication\lvboqi_xmdf.tcl (3147, 2013-04-26)
CooperativeCommunication\M1.v (1547, 2013-04-26)
CooperativeCommunication\M2.v (1290, 2013-04-26)
... ...
The following files were generated for 'lvboqi' in directory
E:\Xilinx\CooperativeCommunication:
lvboqi.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
lvboqi.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
lvboqi.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
lvboqi.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
lvboqi.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
lvboqi.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
lvboqi.sym:
Please see the core data sheet.
lvboqi.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
lvboqi.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
lvboqi_xmdf.tcl:
Please see the core data sheet.
lvboqi_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
lvboqi_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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