RISC-CPU
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3211KB
下载次数：21
上传日期：2013-03-28 19:23:42
上 传 者：
feiyuliuhen
说明： 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写 含有测试平台
(Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains)
文件列表:
RISC-CPU\.nclaunch.dd (2880, 2013-01-01)
RISC-CPU\.nclaunch.dd.bak (2880, 2013-01-01)
RISC-CPU\.simvision\dbrowser-bookmarks (0, 2013-01-01)
RISC-CPU\.simvision\schematic-bookmarks (0, 2013-01-01)
RISC-CPU\.simvision\source-bookmarks (0, 2013-01-01)
RISC-CPU\accum.v (258, 2012-12-30)
RISC-CPU\addr.v (170, 2012-12-30)
RISC-CPU\alu_out.ddc (28928, 2012-12-30)
RISC-CPU\alu_out.v (1301, 2012-12-27)
RISC-CPU\cds.lib (160, 2013-01-01)
RISC-CPU\choose.v (165, 2012-12-28)
RISC-CPU\clkgen.v (864, 2012-12-31)
RISC-CPU\command.log (354874, 2013-01-01)
RISC-CPU\counter.v (300, 2012-12-30)
RISC-CPU\cpu.txt (621, 2012-12-30)
RISC-CPU\cpu.v (1652, 2012-12-31)
RISC-CPU\datactl.v (144, 2012-12-30)
RISC-CPU\data_choose.v (173, 2012-12-30)
RISC-CPU\default.svf (8448, 2012-12-31)
RISC-CPU\filenames.log (7159, 2013-01-01)
RISC-CPU\hdl.var (67, 2012-12-29)
RISC-CPU\INCA_libs\worklib\.cdsvmod (0, 2013-01-01)
RISC-CPU\INCA_libs\worklib\.inca.db.179.lnx86 (8, 2013-01-01)
RISC-CPU\INCA_libs\worklib\inca.lnx86.179.pak (709230, 2013-01-01)
RISC-CPU\machine.v (4864, 2012-12-30)
RISC-CPU\ncelab.log (212, 2013-01-01)
RISC-CPU\nclaunch.key (928, 2013-01-01)
RISC-CPU\ncsim.key (508, 2013-01-01)
RISC-CPU\ncsim.log (965, 2013-01-01)
RISC-CPU\ncvlog.log (210, 2013-01-01)
RISC-CPU\ram.v (1158, 2012-12-31)
RISC-CPU\register.v (710, 2012-12-29)
RISC-CPU\RSUC.v (311741, 2012-12-31)
RISC-CPU\tb.v (576, 2012-12-31)
RISC-CPU\typical.db (5409440, 2011-09-26)
RISC-CPU\umc18\.cdsvmod (0, 2013-01-01)
RISC-CPU\umc18\.inca.db.179.lnx86 (8, 2013-01-01)
RISC-CPU\umc18\inca.lnx86.179.pak (4396524, 2013-01-01)
RISC-CPU\umc18.sdb (414214, 2011-09-26)
RISC-CPU\umc18.v (828799, 2011-09-26)
... ...
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