wtut_ver
所属分类：VHDL/FPGA/Verilog
开发工具：C++ Builder
文件大小：455KB
下载次数：4
上传日期：2013-04-01 20:50:32
上 传 者：
涂海华
说明： Verilog语言开发环境ISE例程，适合于初学者ISE Verilog language development environment routines, suitable for beginners
(For the Verilog language development environment ISE routine suitable for beginners ISE Verilog language development environment routines, suitable for beginners)
文件列表:
wtut_ver (0, 2011-02-10)
wtut_ver\clk_div_262k.v (921, 2011-02-03)
wtut_ver\create_wtut_ver.tcl (605, 2007-03-15)
wtut_ver\definition1_times.coe (1469, 2007-02-23)
wtut_ver\lcd_control.v (31650, 2011-02-03)
wtut_ver\statmach.v (6668, 2007-03-05)
wtut_ver\stopwatch.v (3139, 2011-02-03)
wtut_ver\stopwatch_tb.v (1361, 2011-02-03)
wtut_ver\time_cnt.v (4715, 2011-02-03)
wtut_ver\wtut_ver_completed (0, 2011-02-10)
wtut_ver\wtut_ver_completed\clk_div_262k.v (921, 2011-02-03)
wtut_ver\wtut_ver_completed\debounce.v (688, 2011-02-03)
wtut_ver\wtut_ver_completed\definition1_times.coe (1469, 2007-02-23)
wtut_ver\wtut_ver_completed\ipcore_dir (0, 2011-02-10)
wtut_ver\wtut_ver_completed\ipcore_dir\coregen.cgc (10497, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\coregen.cgp (247, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\dcm1.v (2868, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\dcm1.vhd (3083, 2009-06-24)
wtut_ver\wtut_ver_completed\ipcore_dir\dcm1.xaw (3122, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\dcm1_arwz.ucf (729, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\dcm1_flist.txt (51, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\dist_mem_gen_ds322.pdf (747959, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.asy (263, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.gise (1593, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.ise (10997, 2009-06-26)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.mif (1408, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.ncf (0, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.ngc (16530, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.sym (840, 2009-06-24)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.v (5605, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.veo (4556, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.vhd (5890, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.vho (4942, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.xco (2020, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset.xise (5292, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset_flist.txt (369, 2011-02-03)
wtut_ver\wtut_ver_completed\ipcore_dir\timer_preset_upgrade.txt (163, 2011-02-03)
... ...
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This zip file contains the design files for the 13.1 ISE In-Depth
Tutorial (UG695) - Verilog design flow.
Installation instructions
--------------------------
Unzip the file into a directory with Read/Write permissions.
Documentation
-------------
Refer to the 13.1 ISE In-Depth Tutorial (UG695) available at:
http://www.xilinx.com/support/documentation/dt_ise13-1_tutorials.htm
For support information and contacts please see:
http://www.xilinx.com/support
or
http://www.xilinx.com/support/services/contact_info.htm
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