7segment-display-VHDL
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：166KB
下载次数：4
上传日期：2013-04-07 23:29:54
上 传 者：
chli1107
说明： 使用的NEXYS2原型设计电路板的7段编码器模拟
(using the NEXYS 2 prototyping board Simulate the 7-segment encoder)
文件列表:
7segment display VHDL (0, 2013-04-07)
7segment display VHDL\lab (0, 2013-04-07)
7segment display VHDL\lab\counter.vhd (1300, 2012-05-10)
7segment display VHDL\lab\counter_t.fdo (349, 2012-05-10)
7segment display VHDL\lab\counter_t.udo (112, 2012-05-10)
7segment display VHDL\lab\counter_t.vhd (2249, 2012-05-10)
7segment display VHDL\lab\counter_t_wave.fdo (129, 2012-05-10)
7segment display VHDL\lab\ipcore_dir (0, 2013-04-07)
7segment display VHDL\lab\lab.gise (4016, 2012-05-10)
7segment display VHDL\lab\lab.ise (0, 2013-04-01)
7segment display VHDL\lab\lab.xise (3849, 2012-05-10)
7segment display VHDL\lab\lab_xdb (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise.lock (71, 2013-04-01)
7segment display VHDL\lab\lab_xdb\tmp\ise\version (138, 2013-04-01)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__ (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\Autonym (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\common (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject (201, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject_StrTbl (26, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\__stored_object_table__ (60, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\PnAutoRun (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\PnAutoRun\Scripts (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl (27, 2012-05-16)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl_StrTbl (3817, 2012-05-16)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigator (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigator11 (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui (0, 2013-04-07)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CViewSelector (27, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CViewSelector_StrTbl (33, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\File-SynthesisOnly (63, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\File-SynthesisOnly_StrTbl (11, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Library-SynthesisOnly (61, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Library-SynthesisOnly_StrTbl (16, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Process-BehavioralSim- (63, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE (63, 2012-05-14)
7segment display VHDL\lab\lab_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE_StrTbl (87, 2012-05-14)
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