说明：  This document provides implementation instructions for the DDR3 interface
(This document provides implementation instructions for the DDR3 interface incorporated in the Texas Instruments (TI) Keystone series of DSP devices. It supports 1333 MT/s and higher memory speeds in a variety of topologies (refer to the Data Manual for supported speeds). This document assumes the user has a familiarization with DRAM implementation concepts and constraints. When searching for a particular configuration refer to the appendix, which will alleviate the need for searching the entire document which contains all possible variations.)