Altera-FPGA_CPLD-design
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：8800KB
下载次数：19
上传日期：2013-04-10 16:45:04
上 传 者：
jack1984
说明： 《Altera FPGA-CPLD设计》一书的实例源代码。非常适合FPGA初学者。
(" Altera FPGA-CPLD design" book source code examples. Very suitable for FPGA beginners.)
文件列表:
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\core\myfifo_10.v (7567, 2004-06-12)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\core\myfifo_10_bb.v (1723, 2004-06-12)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\core\myfifo_10_wave0.jpg (102254, 2004-06-12)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\core\myfifo_10_waveforms.html (816, 2004-06-12)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\core\myfifo_8.v (7548, 2004-06-12)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\core\myfifo_8_bb.v (1722, 2004-06-12)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\core\myfifo_8_wave0.jpg (102254, 2004-06-12)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\core\myfifo_8_waveforms.html (810, 2004-06-12)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\chip_editor.acv (78, 2005-01-14)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\cmp_state.ini (2, 2005-01-15)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\add_sub_1jh.tdf (5811, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\add_sub_dhh.tdf (3077, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\add_sub_ehh.tdf (3279, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\add_sub_fhh.tdf (3481, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\add_sub_ihh.tdf (4088, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\add_sub_rih.tdf (4509, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\altsyncram_apb1.tdf (17739, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\altsyncram_mmb1.tdf (15009, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\a_dpfifo_4nl.tdf (4078, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\a_dpfifo_rll.tdf (4083, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\a_fefifo_qve.tdf (4291, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\dpram_81k.tdf (2784, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\dpram_h2k.tdf (2785, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\scfifo_eaq.tdf (2943, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\scfifo_nbq.tdf (2938, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(0).cnf.cdb (15893, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(0).cnf.hdb (2808, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(1).cnf.cdb (9372, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(1).cnf.hdb (1282, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(10).cnf.cdb (2293, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(10).cnf.hdb (625, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(11).cnf.cdb (1099, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(11).cnf.hdb (521, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(12).cnf.cdb (2024, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(12).cnf.hdb (668, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(13).cnf.cdb (13405, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(13).cnf.hdb (2098, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(14).cnf.cdb (1462, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(14).cnf.hdb (598, 2004-12-31)
Altera FPGA-CPLD设计\Example-b3-1\uart_regs\dev\db\uart_regs(15).cnf.cdb (1098, 2004-12-31)
... ...
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