PCI_arbi

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:3KB
下载次数:4
上传日期:2013-04-10 16:49:48
上 传 者jack1984
说明:  PCI总线仲裁参考设计Verilog代码。最大支持6个master的仲裁。
(PCI bus arbitration reference design Verilog code. Maximum six master arbitration.)

文件列表:
PCI_arbi\PCI_ARBI.TF (882, 1999-02-01)
PCI_arbi\Pci_arbi.v (7933, 1999-01-12)
PCI_arbi (0, 2011-08-31)

fpga reference design Offer:QuickLogic PCI Arbiter: Files: \APPS\pci arbiter\pci_arb.exe PCI Master/Target Design: Files: \APPS\PCI\MASTER\*.* Top Level Design: TOP.SCH Simulation Test Fixture: TOP.TF (Verilog HDL Format) Schematic-Based Design with Verilog Sub-Blocks Utilization 583 of 768 logic cells, QL24x32B pASIC 1 device 480 of 672 logic cells, QL2009 pASIC 2 device 123 pins (recommended pinout available, see synthesis constraint file TOP.SC) Overview This application note describes a fully PCI-compliant Master/Slave interface. It utilizes the PCI burst transfer mode for transfers at high speed, up to 67 MBytes per second. Although it is designed to interface the Seeq 80C300 Ethernet Data Link Controller to the PCI bus, it can be easily modified to interface with other peripherals. Data is transferred between System Memory and the Ethernet controller in bursts of eight using Master Mode DMA. Internal 80C300 programming registers are mapped into host memory space and are accessed using slave mode. for more information please visite:www.fpga.com.cn/freeip.htm and www.quicklogic.com

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