EP3C10_Verilog
所属分类：单片机开发
开发工具：C/C++
文件大小：26447KB
下载次数：8
上传日期：2013-04-11 13:46:40
上 传 者：
aipas
说明： ALTERA Cyclone ΙΙΙ EP3C10 开发板测试代码
(ALTERA Cyclone ΙΙΙ EP3C10 development board test code)
文件列表:
EP3C10_Verilog\DS18B20_ysd\db\add_sub_3dc.tdf (1706, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_4dc.tdf (1851, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_5dc.tdf (1476, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_6dc.tdf (1476, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_7dc.tdf (1476, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_8dc.tdf (1476, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_9dc.tdf (1476, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_adc.tdf (1476, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_ke8.tdf (1680, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_le8.tdf (1825, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_ma8.tdf (2331, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_me8.tdf (2095, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_ne8.tdf (2252, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_oe8.tdf (2409, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_pe8.tdf (2566, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_qa8.tdf (2959, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_qe8.tdf (2723, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\add_sub_re8.tdf (2880, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\alt_u_div_6oe.tdf (8149, 2009-09-07)
EP3C10_Verilog\DS18B20_ysd\db\alt_u_div_eoe.tdf (10414, 2009-09-07)
EP3C10_Verilog\DS18B20_ysd\db\alt_u_div_hld.tdf (9677, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\alt_u_div_pld.tdf (12403, 2009-03-28)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(0).cnf.cdb (1462, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(0).cnf.hdb (758, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(1).cnf.cdb (7081, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(1).cnf.hdb (1538, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(10).cnf.cdb (865, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(10).cnf.hdb (511, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(11).cnf.cdb (882, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(11).cnf.hdb (518, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(12).cnf.cdb (915, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(12).cnf.hdb (519, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(13).cnf.cdb (951, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(13).cnf.hdb (525, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(14).cnf.cdb (971, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(14).cnf.hdb (528, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(15).cnf.cdb (998, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(15).cnf.hdb (531, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(16).cnf.cdb (1054, 2009-09-13)
EP3C10_Verilog\DS18B20_ysd\db\DS18B20.(16).cnf.hdb (526, 2009-09-13)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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