Lab08
所属分类:VHDL/FPGA/Verilog
开发工具:LabView
文件大小:1746KB
下载次数:13
上传日期:2013-04-15 10:18:54
上 传 者:
a800005217
说明: LabVIEW FPGA Implementation of Digital Filtering
文件列表:
Lab08 (0, 2010-12-13)
Lab08\filt_dsgn.vi (22417, 2010-06-15)
Lab08\FIR_filter.aliases (48, 2010-12-10)
Lab08\FIR_filter.lvlps (86, 2010-12-10)
Lab08\FIR_filter.lvproj (657523, 2010-12-10)
Lab08\Fir_FPGA_Xilinx_coregen.vi (53795, 2010-12-10)
Lab08\fir_host.fds (2084, 2010-01-04)
Lab08\Fir_hst_Xilinx_coregen.vi (219130, 2010-12-10)
Lab08\sig_gen.vi (37131, 2010-06-15)
Lab08\wrt_ceoff.vi (16997, 2010-06-15)
Lab08\xilinx_coregen (0, 2010-12-13)
Lab08\xilinx_coregen\coregen_fir.cgp (569, 2010-01-04)
Lab08\xilinx_coregen\core_resources.txt (21, 2010-01-12)
Lab08\xilinx_coregen\fir.coe (540, 2010-01-25)
Lab08\xilinx_coregen\fir_compiler_v4_0.dll (717806, 2010-01-26)
Lab08\xilinx_coregen\fir_compiler_v4_0.mif (990, 2010-01-12)
Lab08\xilinx_coregen\fir_compiler_v4_0.ngc (207086, 2010-01-12)
Lab08\xilinx_coregen\fir_compiler_v4_0.vhd (4986, 2010-01-12)
Lab08\xilinx_coregen\fir_compiler_v4_0.vho (3391, 2010-01-12)
Lab08\xilinx_coregen\fir_compiler_v4_0.xco (2540, 2010-01-12)
Lab08\xilinx_coregen\fir_compiler_v4_0COEFF_auto0_0.mif (594, 2010-01-12)
Lab08\xilinx_coregen\fir_compiler_v4_0COEFF_auto0_1.mif (162, 2010-01-06)
Lab08\xilinx_coregen\fir_compiler_v4_0COEFF_auto0_2.mif (162, 2010-01-06)
Lab08\xilinx_coregen\fir_compiler_v4_0COEFF_auto0_3.mif (162, 2010-01-06)
Lab08\xilinx_coregen\fir_compiler_v4_0filt_decode_rom.mif (119, 2010-01-12)
Lab08\xilinx_coregen\fir_compiler_v4_0_fir_compiler_v4_0_xst_1.ngc_xst.xrpt (6183, 2010-01-12)
Lab08\xilinx_coregen\fir_compiler_v4_0_fir_compiler_v4_0_xst_1_vhdl.prj (15339, 2010-01-12)
Lab08\xilinx_coregen\fir_compiler_v4_0_flist.txt (422, 2010-01-12)
Lab08\xilinx_coregen\fir_compiler_v4_0_xmdf.tcl (3590, 2010-01-12)
Lab08\xilinx_coregen\isim (0, 2010-12-13)
Lab08\xilinx_coregen\isim\work (0, 2010-12-13)
Lab08\xilinx_coregen\isim\work\fir_compiler_v4_0.vdb (6475, 2010-01-26)
Lab08\xilinx_coregen\isim\_tmp (0, 2010-12-13)
Lab08\xilinx_coregen\isim\_tmp\ieee (0, 2010-12-13)
Lab08\xilinx_coregen\isim\_tmp\ieee\p_0017514958.didat (3440, 2010-01-26)
Lab08\xilinx_coregen\isim\_tmp\ieee\p_0774719531.didat (2032, 2010-01-26)
Lab08\xilinx_coregen\isim\_tmp\ieee\p_1242562249.didat (8052, 2010-01-26)
Lab08\xilinx_coregen\isim\_tmp\ieee\p_1367372525.didat (13488, 2010-01-26)
Lab08\xilinx_coregen\isim\_tmp\ieee\p_2592010699.didat (5180, 2010-01-26)
... ...
The following files were generated for 'fir_compiler_v4_0' in directory
C:\NIFPGA2009\Ipnode_projects\fir\HOST-fpga(USING ip)\xilinx_coregen\:
core_resources.txt:
Please see the core data sheet.
fir_compiler_v4_0.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
fir_compiler_v4_0.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
fir_compiler_v4_0.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
fir_compiler_v4_0.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
fir_compiler_v4_0.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
fir_compiler_v4_0COEFF_auto0_0.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
fir_compiler_v4_0_fir_compiler_v4_0_xst_1.ngc_xst.xrpt:
Please see the core data sheet.
fir_compiler_v4_0_fir_compiler_v4_0_xst_1_vhdl.prj:
Please see the core data sheet.
fir_compiler_v4_0_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
fir_compiler_v4_0_readme.txt:
Text file indicating the files generated and how they are used.
fir_compiler_v4_0_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
fir_compiler_v4_0filt_decode_rom.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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