5.4_AudioFilter
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：7581KB
下载次数：8
上传日期：2013-04-23 09:55:21
上 传 者：
JustinBieber
说明： 基于SystemGenerator的音频滤波器，实现后可以在SPARTAN6中运行。
(Based on the audio SystemGenerator filter implemented in SPARTAN6 run.)
文件列表:
5.4_AudioFilter\5.4.2_Reverb\audio.wav (68, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\adder_subtracter_spartan3e_7_0_50040490dc45f8ae.edn (27158, 2009-01-14)
5.4_AudioFilter\5.4.2_Reverb\netlist\adder_subtracter_spartan3e_7_0_50040490dc45f8ae.ngo (10031, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\adder_subtracter_spartan3e_7_0_c3896c9d75f6c5f5.edn (48155, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\adder_subtracter_spartan3e_7_0_c3896c9d75f6c5f5.ngo (20888, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\device_usage_statistics.html (52034, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\globals (1268, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\hdlFiles (25, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\multiplier_spartan3e_10_1_533342f9403abe12.edn (14790, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\multiplier_spartan3e_10_1_533342f9403abe12.ngo (8674, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\multiplier_spartan3e_10_1_533342f9403abe12_mult_gen_v10_1_xst_1.ngc (18437, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\multiplier_spartan3e_10_1_ba56673e63880e9c.edn (14790, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\multiplier_spartan3e_10_1_ba56673e63880e9c.ngo (8674, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\multiplier_spartan3e_10_1_ba56673e63880e9c_mult_gen_v10_1_xst_1.ngc (18437, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\name_translations (2395, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb.vhd (123771, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.bgn (4611, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.bit (283869, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.bld (4274, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.cmd_log (1418, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.drc (131, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.ise (242253, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.lso (6, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.ncd (570711, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.ngc (1163069, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.ngd (1636916, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.ngr (986397, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.ntrc_log (122, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.pad (14143, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.par (4279, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.pcf (502307, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.prj (51, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.ptwx (16849, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.restore (58723, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.sdc (47, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.sgp (0, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.stx (0, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.syr (86543, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.twr (18792, 2009-03-25)
5.4_AudioFilter\5.4.2_Reverb\netlist\reverb_cw.twx (37977, 2009-03-25)
... ...
The following files were generated for 'multiplier_spartan3e_10_1_533342f9403abe12' in directory
.\:
multiplier_spartan3e_10_1_533342f9403abe12.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
multiplier_spartan3e_10_1_533342f9403abe12.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
multiplier_spartan3e_10_1_533342f9403abe12.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
multiplier_spartan3e_10_1_533342f9403abe12.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
multiplier_spartan3e_10_1_533342f9403abe12.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
multiplier_spartan3e_10_1_533342f9403abe12.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
multiplier_spartan3e_10_1_533342f9403abe12_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
multiplier_spartan3e_10_1_533342f9403abe12_mult_gen_v10_1_xst_1.ndf:
Optional output file produced for cores that generate NGC files.
The NDF files allow third party synthesis tools to infer resource
utilization and timing from the NGC files associated with these new
cores.
multiplier_spartan3e_10_1_533342f9403abe12_mult_gen_v10_1_xst_1.ngc:
Binary Xilinx implementation netlist. The logic implementation of
certain CORE Generator IP is described by a combination of a top
level EDN file plus one or more NGC files.
multiplier_spartan3e_10_1_533342f9403abe12_mult_gen_v10_1_xst_1.ngc_xst.xrpt:
Please see the core data sheet.
multiplier_spartan3e_10_1_533342f9403abe12_readme.txt:
Text file indicating the files generated and how they are used.
multiplier_spartan3e_10_1_533342f9403abe12_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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