sine-wave
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1157KB
下载次数：3
上传日期：2013-05-06 09:06:46
上 传 者：
BilleYang
说明： spartan-3an sine wave 波形通过dac显示 可改变sweep rate
(spartan-3an sine wave based on VHDL)
文件列表:
sine wave (0, 2013-05-03)
sine wave\data_add (0, 2013-05-03)
sine wave\data_add\data_add (0, 2013-05-03)
sine wave\data_add\data_add\data_add.gise (1059, 2013-04-20)
sine wave\data_add\data_add\data_add.vhd (1365, 2013-04-20)
sine wave\data_add\data_add\data_add.xise (40043, 2013-04-20)
sine wave\data_add\data_add\data_add_summary.html (3533, 2013-04-20)
sine wave\data_add\data_add\ipcore_dir (0, 2013-04-20)
sine wave\data_add\data_add\iseconfig (0, 2013-05-03)
sine wave\data_add\data_add\iseconfig\data_add.projectmgr (4694, 2013-04-20)
sine wave\data_add\data_add\iseconfig\data_add.xreport (20581, 2013-04-20)
sine wave\data_add\data_add\_xmsgs (0, 2013-05-03)
sine wave\data_add\data_add\_xmsgs\pn_parser.xmsgs (762, 2013-04-20)
sine wave\DDS (0, 2013-05-03)
sine wave\DDS\dds_coregen.cgc (30237, 2013-04-19)
sine wave\DDS\dds_coregen.cgp (521, 2013-04-19)
sine wave\DDS\dds_sine (0, 2013-05-03)
sine wave\DDS\dds_sine.asy (353, 2013-04-19)
sine wave\DDS\dds_sine.gise (1264, 2013-04-19)
sine wave\DDS\dds_sine.ngc (86232, 2013-04-19)
sine wave\DDS\dds_sine.vhd (6084, 2013-04-19)
sine wave\DDS\dds_sine.vho (4920, 2013-04-19)
sine wave\DDS\dds_sine.xco (3544, 2013-04-19)
sine wave\DDS\dds_sine.xise (40263, 2013-04-19)
sine wave\DDS\dds_sine\doc (0, 2013-05-03)
sine wave\DDS\dds_sine\doc\dds_compiler_v4_0_vinfo.html (12752, 2013-04-19)
sine wave\DDS\dds_sine\doc\dds_ds558.pdf (1035823, 2013-04-19)
sine wave\DDS\dds_sine_flist.txt (270, 2013-04-19)
sine wave\DDS\dds_sine_xmdf.tcl (2875, 2013-04-19)
sine wave\DDS\tmp (0, 2013-05-03)
sine wave\DDS\tmp\dds_sine_dds_compiler_v4_0_xst_1.lso (6, 2013-04-19)
sine wave\DDS\tmp\_cg (0, 2013-04-19)
sine wave\DDS\tmp\_xmsgs (0, 2013-05-03)
sine wave\DDS\tmp\_xmsgs\pn_parser.xmsgs (746, 2013-04-19)
sine wave\DDS\tmp\_xmsgs\xst.xmsgs (28437, 2013-04-19)
sine wave\DDS\xlnx_auto_0_xdb (0, 2013-04-19)
sine wave\send (0, 2013-05-03)
sine wave\send\send (0, 2013-05-03)
sine wave\send\send\ipcore_dir (0, 2013-04-19)
... ...
The following files were generated for 'dds_sine' in directory
I:\ELE4ADD\DDS\
Generate XCO file:
CORE Generator input file containing the parameters used to generate a core.
* dds_sine.xco
Generate Implementation Netlist:
Binary Xilinx implementation netlist files containing the information
required to implement the module in a Xilinx (R) FPGA.
* dds_sine.ngc
* dds_sine.vhd
Obfuscate Netlist Generator:
Please see the core data sheet.
* dds_sine.ngc
Generate Instantiation Templates:
Template files containing code that can be used as a model for instantiating
a CORE Generator module in an HDL design.
* dds_sine.vho
RTL Simulation Model Generator:
Please see the core data sheet.
* dds_sine.vhd
All Documents Generator:
Please see the core data sheet.
* dds_sine/doc/dds_compiler_v4_0_vinfo.html
* dds_sine/doc/dds_ds558.pdf
Deliver IP Symbol:
Graphical symbol information file. Used by the ISE tools and some third party
tools to create a symbol representing the core.
* dds_sine.asy
Generate XMDF file:
ISE Project Navigator interface file. ISE uses this file to determine how the
files output by CORE Generator for the core can be integrated into your ISE
project.
* dds_sine_xmdf.tcl
Generate ISE project file:
ISE Project Navigator support files. These are generated files and should not
be edited directly.
* dds_sine.gise
* dds_sine.xise
Deliver Readme:
Readme file for the IP.
* dds_sine_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* dds_sine_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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