VHDL_Development_Board_Sources
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：4534KB
下载次数：553
上传日期：2006-11-06 13:06:02
上 传 者：
jawen
说明： 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.
(which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.)
文件列表:
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.asm.rpt (6864, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.bdf (13661, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.cdf (285, 2006-07-03)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.done (26, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.fit.eqn (49264, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.fit.rpt (282689, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.fit.summary (339, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.flow.rpt (3384, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.map.eqn (48247, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.map.rpt (24561, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.map.summary (310, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.pin (12795, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.pof (7998, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.qpf (1567, 2005-11-01)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.qsf (3112, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.qws (1552, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.tan.rpt (71134, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock.tan.summary (1448, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\clock_assignment_defaults.qdf (34961, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\cmp_state.ini (2, 2006-10-23)
VHDL_Development_Board_Sources\综合实验\数字时钟\decode47.bsf (1646, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\decode47.vhd (1274, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\fen1.bsf (1791, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\fen1.vhd (948, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\fen100.bsf (1793, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\fen100.vhd (981, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\fen24.bsf (2198, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\fen24.vhd (1360, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\fen60.bsf (2198, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\fen60.vhd (1178, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\lpm_counter0.bsf (1984, 2006-04-04)
VHDL_Development_Board_Sources\综合实验\数字时钟\lpm_counter0.cmp (957, 2006-04-04)
VHDL_Development_Board_Sources\综合实验\数字时钟\lpm_counter0.vhd (4154, 2006-04-04)
VHDL_Development_Board_Sources\综合实验\数字时钟\lpm_counter0_wave0.jpg (50063, 2006-04-04)
VHDL_Development_Board_Sources\综合实验\数字时钟\lpm_counter0_waveforms.html (549, 2006-04-04)
VHDL_Development_Board_Sources\综合实验\数字时钟\sel.bsf (3175, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\sel.vhd (2065, 2005-12-09)
VHDL_Development_Board_Sources\综合实验\数字时钟\serv_req_info.txt (525, 2006-04-04)
VHDL_Development_Board_Sources\综合实验\数字时钟\talkback\clock.asm.talkback.xml (4014, 2006-07-03)
VHDL_Development_Board_Sources\综合实验\数字时钟\talkback\clock.fit.talkback.xml (15824, 2006-07-03)
... ...
近期下载者：
相关文件：
收藏者：