文件列表:

processor vhdl (0, 2007-10-07)
processor vhdl\dsp320vc33_20020210 (0, 2007-10-07)
processor vhdl\dsp320vc33_20020210\dsp320vc33 (0, 2007-10-07)
processor vhdl\dsp320vc33_20020210\dsp320vc33\dsp320vc33.ftm (2170, 2001-12-24)
processor vhdl\dsp320vc33_20020210\dsp320vc33\dsp320vc33.vec (2493, 2002-02-11)
processor vhdl\dsp320vc33_20020210\dsp320vc33\dsp320vc33.vhd (156562, 2002-02-11)
processor vhdl\dsp320vc33_20020210\dsp320vc33\sram16k32.vhd (28512, 2001-12-10)
processor vhdl\dsp320vc33_20020210\dsp320vc33\sram1k32.vhd (26859, 2002-01-06)
processor vhdl\dsp320vc33_20020210\dsp320vc33\tbdsp320vc33.sdf (1125, 2001-12-16)
processor vhdl\dsp320vc33_20020210\dsp320vc33\tbdsp320vc33.vhd (42928, 2002-02-11)
processor vhdl\dsp6211_20001105 (0, 2007-10-07)
processor vhdl\dsp6211_20001105\dsp6211 (0, 2007-10-07)
processor vhdl\dsp6211_20001105\dsp6211\conpack.vhd (10255, 1999-12-26)
processor vhdl\dsp6211_20001105\dsp6211\dsp6211.ftm (1770, 2000-11-06)
processor vhdl\dsp6211_20001105\dsp6211\dsp6211.vec (2106, 2000-06-12)
processor vhdl\dsp6211_20001105\dsp6211\dsp6211.vhd (196743, 2000-11-06)
processor vhdl\dsp6211_20001105\dsp6211\km416s4030.vhd (76861, 2000-05-10)
processor vhdl\dsp6211_20001105\dsp6211\mt58l32l32p.vhd (12155, 1999-12-26)
processor vhdl\dsp6211_20001105\dsp6211\mti_pkg.vhd (3998, 2000-05-11)
processor vhdl\dsp6211_20001105\dsp6211\sram1k16.vhd (22430, 1999-12-26)
processor vhdl\dsp6211_20001105\dsp6211\sram1k8.vhd (20053, 1999-12-26)
processor vhdl\dsp6211_20001105\dsp6211\tbdsp6211.sdf (4026, 2000-11-06)
processor vhdl\dsp6211_20001105\dsp6211\tbdsp6211.vhd (87542, 2000-11-06)
processor vhdl\dsp6415_20021117 (0, 2007-10-07)
processor vhdl\dsp6415_20021117\dsp6415 (0, 2007-10-07)
processor vhdl\dsp6415_20021117\dsp6415\Ms32pci.vhd (40110, 2002-09-08)
processor vhdl\dsp6415_20021117\dsp6415\PCI.CMD (2644, 2002-06-23)
processor vhdl\dsp6415_20021117\dsp6415\PCI.vec (3587, 2002-11-11)
processor vhdl\dsp6415_20021117\dsp6415\Pci_lib.vhd (35574, 2002-09-08)
processor vhdl\dsp6415_20021117\dsp6415\at9366.vhd (24575, 2002-09-08)
processor vhdl\dsp6415_20021117\dsp6415\conpack.vhd (10254, 2002-09-08)
processor vhdl\dsp6415_20021117\dsp6415\cy7c453.vhd (44754, 2002-06-23)
processor vhdl\dsp6415_20021117\dsp6415\dsp6415.ftm (10411, 2002-11-14)
processor vhdl\dsp6415_20021117\dsp6415\dsp6415.vec (18290, 2002-11-11)
processor vhdl\dsp6415_20021117\dsp6415\dsp6415.vhd (832342, 2002-11-11)
processor vhdl\dsp6415_20021117\dsp6415\idt71v546.vhd (66548, 2002-06-23)
processor vhdl\dsp6415_20021117\dsp6415\km416s4030.vhd (76950, 2002-06-23)
... ...

GM HC11 CPU Core v0.1. (c) Green Mountain Computing Systems, Inc., 2000 This package consists of a fully-synthesizable VHDL model of the HC11 CPU, several testbench files, and a simple HC11 debugger. The CPU implements all instructions except the two divide instructions (note: although the DAA instruction is implemented, it is commented out due to its effect on performance). The package is best used with VHDL Studio. You can download a demo. version of VHDL Studio from http://www.gmvhdl.com/downloads.html. This model may NOT be distributed freely. Please see the terms and conditions of use set forth in license.txt. The following files are included in this package: readme.txt - This file. hc11rtl.vhd, syncore.vhd - This is the synthesizable CPU model. clkgen.vhd, dev.vhd, ram.vhd, srec_rom.vhd, testcore.vhd - These files make up a behavioral testbench that can be used to simulate the execution of an HC11 program on the CPU Core. testprog.prj - This is a VHDL Studio project for the testbench mentioned above. hexout.asm, hexout.s19 - This is a sample HC11 program in assembly and S-record format. rom.s19 - This is a copy of hexout.s19. This file contains the program simulated by the testprog.prj testbench. It can be replaced with any HC11 program. *.wtb - These are self-checking testbenches that test individual instructions of the CPU. These graphical testbenches are best used with VHDL Studio via the corresponding project files. testset?.prj - These are VHDL Studio projects that contain the .wtb files mentioned above. disasm.tcl, hc11.tcl, testbench_behav.tcl - These files make up the simple HC11 debugger for use with the testprog.prj testbench. The debugger will only work with VHDL Studio. The following are some brief instructions for using this model with VHDL Studio. SIMULATING AN HC11 PROGRAM 1) Create a rom.s19 S-record file containing the program machine code. The start address of the program should be stored at $fffe (the reset vector). The rom.s19 file included is the sample hexout.asm program which converts a word to ASCII and sends the output to the serial port. 2) Start VHDL Studio and open the testprog.prj. 3) Push the build toolbar button (stack of papers with two arrows). 4) Select the Debug->Start Simulation menu item. The HC11 Tcl debugger is automatically loaded. 5) Press the gear icon to advance simulation and inspect the signal waveforms. Or, click on the Tk tab to view the HC11 debugger. If you are simulating the hexout.asm program, then you can run the simulation to 130 us (hint: use the Debug->Go menu item) and click on the TextIO tab. This will display the results sent to the serial port by the hexout.asm program. RUNNING THE SELF-CHECKING TESTBENCHES 1) Start VHDL Studio and load any one of the testset?.prj VHDL projects. 2) Double-click on a .wtb file in the project window to open it. The graphical waveform editor will appear with the input stimulus and expected results. The signals with the yellow triangle next to their names are self-checked signals. 3) Click the Run toolbar button in the waveform editor window to run that testbench. A report will appear displaying errors if any.

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