tapcontroller

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:33KB
下载次数:25
上传日期:2013-05-28 17:13:45
上 传 者iamg
说明:  FPGA边界扫描时的TAP控制器,这个是工程文件,带有modelsim仿真
(FPGA boundary scan when the TAP controller, this is a project file with modelsim simulation)

文件列表:
tapcontroller (0, 2013-05-28)
tapcontroller\tapcontroller.cr.mti (269, 2013-05-28)
tapcontroller\tapcontroller.mpf (17851, 2013-05-27)
tapcontroller\tapcontroller.v (2368, 2013-05-27)
tapcontroller\tapcontroller.v.bak (2367, 2013-05-27)
tapcontroller\tapcontroller.vhd.bak (2, 2013-05-27)
tapcontroller\test.v (873, 2013-05-27)
tapcontroller\test.v.bak (663, 2013-05-27)
tapcontroller\vsim.wlf (32768, 2013-05-27)
tapcontroller\wave.do (1984, 2013-05-28)
tapcontroller\work (0, 2013-05-27)
tapcontroller\work\_info (592, 2013-05-27)
tapcontroller\work\_temp (0, 2013-05-28)
tapcontroller\work\_vmake (26, 2013-05-27)
tapcontroller\work\tapcontroller (0, 2013-05-27)
tapcontroller\work\tapcontroller\_primary.dat (1981, 2013-05-27)
tapcontroller\work\tapcontroller\_primary.dbs (11202, 2013-05-27)
tapcontroller\work\tapcontroller\_primary.vhd (575, 2013-05-27)
tapcontroller\work\tapcontroller\verilog.prw (4051, 2013-05-27)
tapcontroller\work\tapcontroller\verilog.psm (20656, 2013-05-27)
tapcontroller\work\test (0, 2013-05-27)
tapcontroller\work\test\_primary.dat (1155, 2013-05-27)
tapcontroller\work\test\_primary.dbs (2950, 2013-05-27)
tapcontroller\work\test\_primary.vhd (68, 2013-05-27)
tapcontroller\work\test\verilog.prw (2476, 2013-05-27)
tapcontroller\work\test\verilog.psm (10056, 2013-05-27)

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