FPGA-SRC
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2760KB
下载次数：19
上传日期：2013-05-30 10:06:23
上 传 者：
tashixuexi
说明： 用于DSP+FPGA开发系统，可用于采集一帧图像并控制SRAM、SDRAM数据存取。
(Used in DSP+ FPGA development system, to capture an image and control the SRAM, SDRAM data access.)
文件列表:
FPGA SRCep2c5release\altpll0.bsf (3457, 2006-10-15)
FPGA SRCep2c5release\altpll0.inc (854, 2006-10-15)
FPGA SRCep2c5release\altpll0.v (10254, 2006-10-15)
FPGA SRCep2c5release\altpll0_bb.v (8702, 2006-10-15)
FPGA SRCep2c5release\altpll0_wave0.jpg (58496, 2006-10-15)
FPGA SRCep2c5release\altpll0_waveforms.html (680, 2008-01-11)
FPGA SRCep2c5release\altpll1.bsf (2986, 2007-08-25)
FPGA SRCep2c5release\altpll1.cmp (902, 2007-08-25)
FPGA SRCep2c5release\altpll1.tdf (7914, 2007-08-25)
FPGA SRCep2c5release\altpll1_wave0.jpg (49121, 2007-08-25)
FPGA SRCep2c5release\altpll1_waveforms.html (691, 2008-01-11)
FPGA SRCep2c5release\bt656gen.bsf (2946, 2011-05-23)
FPGA SRCep2c5release\bt656gen.vhd (2578, 2011-05-23)
FPGA SRCep2c5release\bt656gen.vhd.bak (2578, 2011-05-23)
FPGA SRCep2c5release\clk135.bdf (16752, 2006-10-19)
FPGA SRCep2c5release\cmp_state.ini (2, 2007-01-08)
FPGA SRCep2c5release\cpu_0.ocp (840, 2006-08-20)
FPGA SRCep2c5release\cpu_0.v (190576, 2006-08-20)
FPGA SRCep2c5release\cpu_0_jtag_debug_module.v (11362, 2006-08-20)
FPGA SRCep2c5release\cpu_0_jtag_debug_module_wrapper.v (9543, 2006-08-20)
FPGA SRCep2c5release\cpu_0_ociram_default_contents.mif (5878, 2006-08-20)
FPGA SRCep2c5release\cpu_0_test_bench.v (37640, 2006-08-20)
FPGA SRCep2c5release\db\add_sub_34i.tdf (3375, 2007-08-24)
FPGA SRCep2c5release\db\add_sub_54i.tdf (3720, 2007-08-24)
FPGA SRCep2c5release\db\add_sub_74i.tdf (4062, 2007-08-24)
FPGA SRCep2c5release\db\add_sub_hsh.tdf (3372, 2006-09-07)
FPGA SRCep2c5release\db\add_sub_ish.tdf (3546, 2006-09-07)
FPGA SRCep2c5release\db\add_sub_jsh.tdf (3717, 2006-10-27)
FPGA SRCep2c5release\db\add_sub_o0i.tdf (4916, 2007-08-24)
FPGA SRCep2c5release\db\altsyncram_0u21.tdf (24308, 2006-08-03)
FPGA SRCep2c5release\db\altsyncram_1mq.tdf (9952, 2007-01-06)
FPGA SRCep2c5release\db\altsyncram_2ge1.tdf (23023, 2007-01-08)
FPGA SRCep2c5release\db\altsyncram_4oo1.tdf (2852, 2011-05-23)
FPGA SRCep2c5release\db\altsyncram_9fh1.tdf (22503, 2006-10-27)
FPGA SRCep2c5release\db\altsyncram_9pq1.tdf (43072, 2006-08-04)
FPGA SRCep2c5release\db\altsyncram_alc1.tdf (22653, 2007-01-06)
FPGA SRCep2c5release\db\altsyncram_arv1.tdf (9970, 2006-08-04)
FPGA SRCep2c5release\db\altsyncram_bgs.tdf (8600, 2006-09-08)
FPGA SRCep2c5release\db\altsyncram_bpo1.tdf (2854, 2011-03-04)
FPGA SRCep2c5release\db\altsyncram_cro1.tdf (45747, 2006-08-04)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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