ddr2_v5
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：13171KB
下载次数：77
上传日期：2013-05-31 22:24:53
上 传 者：
Ironpt
说明： 基于FPGA v5的ddr2-sdram控制器的设计verilog
(Based on FPGA v5 of ddr2-sdram controller design verilog)
文件列表:
ddr2_v5\coregen.cgp (531, 2010-10-17)
ddr2_v5\_xmsgs\pn_parser.xmsgs (573, 2010-11-18)
ddr2_v5\mig_v3_5\docs\adr_cntrl_timing.xls (19456, 2010-03-22)
ddr2_v5\mig_v3_5\docs\read_data_timing.xls (24064, 2010-03-22)
ddr2_v5\mig_v3_5\docs\ug086.pdf (15077727, 2010-06-11)
ddr2_v5\mig_v3_5\docs\write_data_timing.xls (18944, 2010-03-22)
ddr2_v5\mig_v3_5\docs\xapp858.url (125, 2010-03-22)
ddr2_v5\mig_v3_5\example_design\datasheet.txt (3369, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\log.txt (6705, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\mig.prj (3046, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\compatible_ucf\xc5vsx50t_ff1136.ucf (22147, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\create_ise.bat (412, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\icon4_cg.xco (1372, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\ise_flow.bat (1234, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\makeproj.bat (28, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\mem_interface_top.ut (724, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\mig_v3_5.cdc (25241, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\mig_v3_5.ucf (22139, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\rem_files.bat (7008, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\set_ise_prop.tcl (9987, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\vio_async_in100_cg.xco (1571, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\vio_async_in192_cg.xco (1571, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\vio_async_in96_cg.xco (1569, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\vio_sync_out32_cg.xco (1569, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\par\xst_run.txt (1165, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_chipscope.v (3472, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_ctrl.v (47008, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_idelay_ctrl.v (3559, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_infrastructure.v (12950, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_mem_if_top.v (15999, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_phy_calib.v (110705, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_phy_ctl_io.v (9968, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_phy_dm_iob.v (3422, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_phy_dq_iob.v (21882, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_phy_dqs_iob.v (8883, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_phy_init.v (49188, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_phy_io.v (14390, 2010-11-18)
ddr2_v5\mig_v3_5\example_design\rtl\ddr2_phy_top.v (17170, 2010-11-18)
... ...
The following files were generated for 'mig_v3_5' in directory
E:\code\ddr2_v5\
mig_v3_5\docs\adr_cntrl_timing.xls:
Please see the core data sheet.
mig_v3_5\docs\read_data_timing.xls:
Please see the core data sheet.
mig_v3_5\docs\ug086.pdf:
Please see the core data sheet.
mig_v3_5\docs\write_data_timing.xls:
Please see the core data sheet.
mig_v3_5\docs\xapp858.url:
Please see the core data sheet.
mig_v3_5_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
mig_v3_5\example_design\datasheet.txt:
Please see the core data sheet.
mig_v3_5\example_design\log.txt:
Please see the core data sheet.
mig_v3_5\example_design\mig.prj:
Please see the core data sheet.
mig_v3_5\example_design\par\compatible_ucf\xc5vsx50t_ff1136.ucf:
Please see the core data sheet.
mig_v3_5\example_design\par\create_ise.bat:
Please see the core data sheet.
mig_v3_5\example_design\par\icon4_cg.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5\example_design\par\ise_flow.bat:
Please see the core data sheet.
mig_v3_5\example_design\par\makeproj.bat:
Please see the core data sheet.
mig_v3_5\example_design\par\mem_interface_top.ut:
Please see the core data sheet.
mig_v3_5\example_design\par\mig_v3_5.cdc:
Please see the core data sheet.
mig_v3_5\example_design\par\mig_v3_5.ucf:
Please see the core data sheet.
mig_v3_5\example_design\par\readme.txt:
Please see the core data sheet.
mig_v3_5\example_design\par\rem_files.bat:
Please see the core data sheet.
mig_v3_5\example_design\par\set_ise_prop.tcl:
Please see the core data sheet.
mig_v3_5\example_design\par\vio_async_in100_cg.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5\example_design\par\vio_async_in192_cg.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5\example_design\par\vio_async_in96_cg.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5\example_design\par\vio_sync_out32_cg.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5\example_design\par\xst_run.txt:
Please see the core data sheet.
mig_v3_5\example_design\rtl\ddr2_chipscope.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_ctrl.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_idelay_ctrl.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_infrastructure.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_mem_if_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_phy_calib.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_phy_ctl_io.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_phy_dm_iob.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_phy_dq_iob.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_phy_dqs_iob.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_phy_init.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_phy_io.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_phy_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_phy_write.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_tb_test_addr_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_tb_test_cmp.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_tb_test_data_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_tb_test_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_tb_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_usr_addr_fifo.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_usr_rd.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_usr_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\ddr2_usr_wr.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\rtl\mig_v3_5.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\sim\ddr2_model.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\sim\ddr2_model_parameters.vh:
Please see the core data sheet.
mig_v3_5\example_design\sim\sim.do:
Please see the core data sheet.
mig_v3_5\example_design\sim\sim_tb_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\sim\wiredly.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\example_design\synth\mem_interface_top_synp.sdc:
Please see the core data sheet.
mig_v3_5\example_design\synth\mig_v3_5.lso:
Please see the core data sheet.
mig_v3_5\example_design\synth\mig_v3_5.prj:
Please see the core data sheet.
mig_v3_5\example_design\synth\script_synp.tcl:
Please see the core data sheet.
mig_v3_5\user_design\datasheet.txt:
Please see the core data sheet.
mig_v3_5\user_design\log.txt:
Please see the core data sheet.
mig_v3_5\user_design\mig.prj:
Please see the core data sheet.
mig_v3_5\user_design\par\compatible_ucf\xc5vsx50t_ff1136.ucf:
Please see the core data sheet.
mig_v3_5\user_design\par\create_ise.bat:
Please see the core data sheet.
mig_v3_5\user_design\par\icon4_cg.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5\user_design\par\ise_flow.bat:
Please see the core data sheet.
mig_v3_5\user_design\par\makeproj.bat:
Please see the core data sheet.
mig_v3_5\user_design\par\mem_interface_top.ut:
Please see the core data sheet.
mig_v3_5\user_design\par\mig_v3_5.cdc:
Please see the core data sheet.
mig_v3_5\user_design\par\mig_v3_5.ucf:
Please see the core data sheet.
mig_v3_5\user_design\par\readme.txt:
Please see the core data sheet.
mig_v3_5\user_design\par\rem_files.bat:
Please see the core data sheet.
mig_v3_5\user_design\par\set_ise_prop.tcl:
Please see the core data sheet.
mig_v3_5\user_design\par\vio_async_in100_cg.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5\user_design\par\vio_async_in192_cg.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5\user_design\par\vio_async_in96_cg.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5\user_design\par\vio_sync_out32_cg.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5\user_design\par\xst_run.txt:
Please see the core data sheet.
mig_v3_5\user_design\rtl\ddr2_chipscope.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_ctrl.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_idelay_ctrl.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_infrastructure.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_mem_if_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_phy_calib.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_phy_ctl_io.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_phy_dm_iob.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_phy_dq_iob.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_phy_dqs_iob.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_phy_init.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_phy_io.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_phy_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_phy_write.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_usr_addr_fifo.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_usr_rd.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_usr_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\ddr2_usr_wr.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\rtl\mig_v3_5.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\sim\ddr2_model.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\sim\ddr2_model_parameters.vh:
Please see the core data sheet.
mig_v3_5\user_design\sim\ddr2_tb_test_addr_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\sim\ddr2_tb_test_cmp.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\sim\ddr2_tb_test_data_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\sim\ddr2_tb_test_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\sim\ddr2_tb_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\sim\sim.do:
Please see the core data sheet.
mig_v3_5\user_design\sim\sim_tb_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\sim\wiredly.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mig_v3_5\user_design\synth\mem_interface_top_synp.sdc:
Please see the core data sheet.
mig_v3_5\user_design\synth\mig_v3_5.lso:
Please see the core data sheet.
mig_v3_5\user_design\synth\mig_v3_5.prj:
Please see the core data sheet.
mig_v3_5\user_design\synth\script_synp.tcl:
Please see the core data sheet.
mig_v3_5.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
mig_v3_5.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
mig_v3_5.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
mig_v3_5.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
mig_v3_5_readme.txt:
Text file indicating the files generated and how they are used.
mig_v3_5_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to det ... ...
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