LOC_NEN
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:942KB
下载次数:7
上传日期:2013-06-07 17:14:47
上 传 者:
lawanhi
说明: This code user for compression and Filter baker signal. This signal userful in Radar system.
文件列表:
LOC_NEN\coregen.cgc (2049, 2011-12-02)
LOC_NEN\coregen.cgp (518, 2011-12-02)
LOC_NEN\gan_chan.ucf (397, 2011-12-02)
LOC_NEN\ipcore_dir\.lso (19, 2011-12-02)
LOC_NEN\ipcore_dir\coregen.cgc (16399, 2011-12-16)
LOC_NEN\ipcore_dir\coregen.cgp (518, 2011-12-16)
LOC_NEN\ipcore_dir\coregen.log (418, 2011-12-16)
LOC_NEN\ipcore_dir\coregen.rsp (211, 2011-12-16)
LOC_NEN\ipcore_dir\dds.asy (422, 2011-12-02)
LOC_NEN\ipcore_dir\dds.cgc (24116, 2011-12-02)
LOC_NEN\ipcore_dir\dds.cgp (521, 2011-12-02)
LOC_NEN\ipcore_dir\dds.gise (1341, 2013-04-09)
LOC_NEN\ipcore_dir\dds.ncf (0, 2011-12-02)
LOC_NEN\ipcore_dir\dds.ngc (50395, 2011-12-02)
LOC_NEN\ipcore_dir\dds.v (73116, 2011-12-02)
LOC_NEN\ipcore_dir\dds.veo (2978, 2011-12-02)
LOC_NEN\ipcore_dir\dds.vhd (4348, 2011-12-02)
LOC_NEN\ipcore_dir\dds.vho (3275, 2011-12-02)
LOC_NEN\ipcore_dir\dds.xco (2659, 2011-12-02)
LOC_NEN\ipcore_dir\dds.xise (4990, 2011-12-02)
LOC_NEN\ipcore_dir\dds_flist.txt (184, 2011-12-02)
LOC_NEN\ipcore_dir\dds_xmdf.tcl (2777, 2011-12-02)
LOC_NEN\ipcore_dir\tmp\_cg (0, 2011-12-16)
LOC_NEN\ipcore_dir\tmp (0, 2011-12-16)
LOC_NEN\ipcore_dir\xlnx_auto_0_xdb (0, 2011-12-02)
LOC_NEN\ipcore_dir\_xmsgs\netgen.xmsgs (665, 2011-12-02)
LOC_NEN\ipcore_dir\_xmsgs\ngcbuild.xmsgs (367, 2011-12-02)
LOC_NEN\ipcore_dir\_xmsgs\pn_parser.xmsgs (956, 2013-04-09)
LOC_NEN\ipcore_dir\_xmsgs\xst.xmsgs (17072, 2011-12-02)
LOC_NEN\ipcore_dir\_xmsgs (0, 2011-12-02)
LOC_NEN\ipcore_dir (0, 2012-01-07)
LOC_NEN\iseconfig\LOC_NEN.projectmgr (6407, 2013-04-09)
LOC_NEN\iseconfig\loc_nen.xreport (19675, 2013-04-09)
LOC_NEN\iseconfig (0, 2011-12-02)
LOC_NEN\loc_nen.bgn (6583, 2011-12-18)
LOC_NEN\loc_nen.bit (1712645, 2011-12-18)
LOC_NEN\loc_nen.bld (1197, 2011-12-18)
LOC_NEN\loc_nen.cmd_log (12280, 2011-12-18)
LOC_NEN\loc_nen.drc (185, 2011-12-18)
... ...
The following files were generated for 'dds' in directory
D:\LOC NEN\LOC_NEN\ipcore_dir\
dds.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
dds.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
dds.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
dds.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
dds.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
dds.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
dds.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
dds.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
dds.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
dds_readme.txt:
Text file indicating the files generated and how they are used.
dds_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
dds_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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