ddc_v5
所属分类：matlab编程
开发工具：matlab
文件大小：649KB
下载次数：51
上传日期：2013-06-11 18:15:53
上 传 者：
ycp007
说明： wcdma数字下变频 是采用matlab 里面的simulink仿真工具和xilinx 的system generator 工作开发的，可以直接运行的，非常有参考价值
(wcdma digital down conversion is used inside matlab simulink simulation tools and working to develop a xilinx system generator, and can run directly, very useful)
文件列表:
ddc\Implementation\Sp3a\ddc_umts_sp3a_init.m (1418, 2007-07-02)
ddc\Implementation\Sp3a\ddc_umts_sp3a_post.m (2942, 2007-05-22)
ddc\Implementation\Sp3a\ddc_umts_sp3a_v1_0.mdl (164943, 2007-08-22)
ddc\Implementation\VHDL\complex_mult_v5.vhd (4561, 2007-08-22)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_h1.coe (174, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1.edn (15992, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1.mif (220, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1.vhd (296261, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1.vho (3300, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1.xco (2249, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1COEFF_auto0.mif (100, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1COEFF_auto_HALFBAND_CENTRE.mif (40, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1filt_decode_rom.mif (68, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1_fir_compiler_v3_0_xst_1.ngc (282071, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1_flist.txt (304, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1_unobf.ngc (286682, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\ddc_hf1_xmdf.tcl (3569, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf1\hex_ddc_hf1.mif (77, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_h2.coe (286, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2.edn (16424, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2.mif (380, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2.vhd (316384, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2.vho (3300, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2.xco (2249, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2COEFF_auto0.mif (180, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2COEFF_auto_HALFBAND_CENTRE.mif (40, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2filt_decode_rom.mif (85, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2_fir_compiler_v3_0_xst_1.ngc (306576, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2_flist.txt (304, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2_unobf.ngc (311405, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\ddc_hf2_xmdf.tcl (3569, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_hf2\hex_ddc_hf2.mif (133, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_srrc\ddc_h3.coe (1350, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_srrc\ddc_srrc.edn (17156, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_srrc\ddc_srrc.mif (1900, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_srrc\ddc_srrc.vhd (528432, 2007-05-09)
ddc\Implementation\VHDL\cores\ddc_srrc\ddc_srrc.vho (3302, 2007-05-09)
... ...
Model directory contains all the matlab simulation model files
Implementation directory contains 3 folders:
Virtex5: WCDMA design files targeting Virtex5 FPGA in System Generator
Sp3a: WCDMA design files targeting Spartan-DSP FPGA in System Generator
VHDL: WCDMA design files using VHDL flow
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