SDRAM_FPGA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2888KB
下载次数：37
上传日期：2013-06-14 22:47:16
上 传 者：
Joling
说明： 这个是SDRAM的控制程序，包括包括UART和FIFO模块，适合FPGA开发人员看，也适合初学者学习。
(This is the SDRAM control procedures, including including UART and FIFO module, suitable for FPGA developers look, but also suitable for beginners to learn.)
文件列表:
ex9 (0, 2013-01-26)
ex9\reference_verilog (0, 2013-01-26)
ex9\reference_verilog\SDRSD50_071010.v (87809, 2007-10-10)
ex9\sdram_mdl (0, 2013-02-19)
ex9\sdram_mdl\PLL_ctrl.bsf (4084, 2013-01-26)
ex9\sdram_mdl\PLL_ctrl.ppf (614, 2013-01-26)
ex9\sdram_mdl\PLL_ctrl.qip (543, 2013-01-26)
ex9\sdram_mdl\PLL_ctrl.v (18223, 2013-01-26)
ex9\sdram_mdl\PLL_ctrl_bb.v (13955, 2013-01-26)
ex9\sdram_mdl\PLL_ctrl_inst.v (162, 2013-01-26)
ex9\sdram_mdl\PLL_ctrl_wave0.jpg (800797, 2009-05-14)
ex9\sdram_mdl\PLL_ctrl_waveforms.html (862, 2009-05-14)
ex9\sdram_mdl\datagene.v (3271, 2009-05-14)
ex9\sdram_mdl\datagene.v.bak (3293, 2009-05-14)
ex9\sdram_mdl\db (0, 2013-02-19)
ex9\sdram_mdl\db\a_fefifo_ctc.tdf (5120, 2009-05-11)
ex9\sdram_mdl\db\a_fefifo_htc.tdf (3359, 2009-05-11)
ex9\sdram_mdl\db\a_gray2bin_q4b.tdf (1640, 2009-05-11)
ex9\sdram_mdl\db\a_graycounter_u06.tdf (2782, 2009-05-11)
ex9\sdram_mdl\db\add_sub_918.tdf (3147, 2013-01-26)
ex9\sdram_mdl\db\add_sub_gub.tdf (3030, 2009-05-11)
ex9\sdram_mdl\db\add_sub_se8.tdf (3042, 2013-01-26)
ex9\sdram_mdl\db\alt_sync_fifo_0fm.tdf (5206, 2009-05-11)
ex9\sdram_mdl\db\alt_sync_fifo_0oi.tdf (5068, 2013-01-26)
ex9\sdram_mdl\db\alt_synch_pipe_oc8.tdf (2094, 2009-05-11)
ex9\sdram_mdl\db\alt_synch_pipe_pc8.tdf (2094, 2009-05-11)
ex9\sdram_mdl\db\altsyncram_1lh1.tdf (20916, 2013-01-26)
ex9\sdram_mdl\db\cntr_cta.tdf (4526, 2009-05-11)
ex9\sdram_mdl\db\cntr_kua.tdf (4759, 2013-01-26)
ex9\sdram_mdl\db\dcfifo_35l1.tdf (7528, 2009-05-11)
ex9\sdram_mdl\db\dcfifo_o2l1.tdf (2924, 2013-01-26)
ex9\sdram_mdl\db\dffpipe_gd9.tdf (1570, 2009-05-11)
ex9\sdram_mdl\db\dffpipe_id9.tdf (1902, 2009-05-11)
ex9\sdram_mdl\db\dffpipe_jd9.tdf (1902, 2009-05-11)
ex9\sdram_mdl\db\dpram_6o31.tdf (2450, 2013-01-26)
ex9\sdram_mdl\db\logic_util_heursitic.dat (25828, 2013-01-26)
ex9\sdram_mdl\db\prev_cmp_sdr_test.asm.qmsg (2007, 2009-09-14)
ex9\sdram_mdl\db\prev_cmp_sdr_test.eda.qmsg (2350, 2009-09-14)
ex9\sdram_mdl\db\prev_cmp_sdr_test.fit.qmsg (67950, 2009-09-14)
... ...
=============================
======== Read Me ========
=============================
File SDRSD50_071010.v is integrated verilog model
for (Mobile) SDRAM(***M, 128M, 256M) of Samsung.
It is protectd using Verilog-XL(Cadence) or VCS.
If you want to simulate verilog behavioral model
then set following option(+define) for products
in verilog command line.
- Density
-***M - +M***
-128M - +M128
-256M - +M256
- Organization
-X4 - +X4
-X8 - +X8
-X16 - +X16
- Speed
-75 - +S75
-60 - +S60
- BANK
-4BANK - +NBANK4
-2BANK - +NBANK2
- Memory allocation
Static - default
Dynamic - +DYMEM (to use dynamic-allocation, you must build
verilog-XL excutable file which contains PLI routines
according to below information)
- If you want print command-echo at log file, use +v option
ex) Product : K4S561632J, -60 (256M, x16bit, 4Banks, -60)
If you want to simulate K4S561632J, -60
then you have to set following command.
Verilog command : verilog +define+M256+X16+S60+NBANK4 SDRSD50_071010.v
-- Power-up time of SDRAM is 200u sec.
So when model check power-up time, simulation time is long.
If you want to skip power-up time checking,
set parameter (powerup_check) to 0;
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