gardner_test
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：7KB
下载次数：125
上传日期：2013-06-21 11:40:21
上 传 者：
lblsword
说明： 无线通信中接收机的位同步，采用的gardner算法实现的verilog程序，需要自己综合编译
(Wireless communication receiver bit synchronization algorithm used gardner the verilog program needs its own comprehensive compilation)
文件列表:
temp_con.v (381, 2011-03-23)
acc.v (803, 2011-03-24)
bit_error_detection.v (1739, 2011-03-23)
bit_error_detection_cut_out.v (163, 2011-03-23)
c1andc2.v (316, 2011-03-23)
cal_err.v (350, 2011-03-23)
dds.v (1244, 2011-03-24)
error_dec.v (951, 2012-10-12)
gardner_test.v (3198, 2012-10-25)
gardner_test_tb.v (2608, 2011-03-24)
level1_add.v (1164, 2011-03-24)
linear_interpolator.v (1199, 2012-10-12)
loop_filter.v (1680, 2012-10-25)
resample_mod.v (393, 2011-03-23)
近期下载者：
相关文件：
收藏者：