DE2_FPGA_IO
所属分类：VHDL/FPGA/Verilog
开发工具：QT
文件大小：325KB
下载次数：1
上传日期：2013-06-25 19:24:29
上 传 者：
363348494
说明： Altera DE2开发板基本输入输出实验，初学者用
(Altera DE2 development board basic input-output experiment,only for beginners)
文件列表:
DE2_firstProjectV1\db (0, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.(0).cnf.cdb (9687, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.(0).cnf.hdb (8351, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.(1).cnf.cdb (1065, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.(1).cnf.hdb (412, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.asm.qmsg (1607, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.cbx.xml (89, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.cmp.qrpt (0, 2006-05-18)
DE2_firstProjectV1\db\DE2_TOP.cmp.rdb (3794, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.db_info (135, 2006-05-18)
DE2_firstProjectV1\db\DE2_TOP.dbp (0, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.eco.cdb (140, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.fit.qmsg (748190, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.hier_info (14569, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.hif (882, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.map.cdb (6889, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.map.hdb (17795, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.map.logdb (4, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.map.qmsg (150487, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.pre_map.cdb (9812, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.pre_map.hdb (23942, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.psp (0, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.rtlv.hdb (23929, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.rtlv_sg.cdb (10109, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.rtlv_sg_swap.cdb (603, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.sgdiff.cdb (6356, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.sgdiff.hdb (25362, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.sld_design_entry.sci (133, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.sld_design_entry_dsc.sci (133, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.syn_hier_info (0, 2006-05-19)
DE2_firstProjectV1\db\DE2_TOP.tan.qmsg (100334, 2006-05-19)
DE2_firstProjectV1\DE2_pin_assignments.csv (8308, 2005-11-16)
DE2_firstProjectV1\DE2_TOP.asm.rpt (9023, 2006-05-19)
DE2_firstProjectV1\DE2_TOP.cdf (284, 2006-05-19)
DE2_firstProjectV1\DE2_TOP.done (26, 2006-05-19)
DE2_firstProjectV1\DE2_TOP.fit.eqn (61421, 2006-05-19)
DE2_firstProjectV1\DE2_TOP.fit.rpt (434655, 2006-05-19)
DE2_firstProjectV1\DE2_TOP.fit.summary (495, 2006-05-19)
DE2_firstProjectV1\DE2_TOP.flow.rpt (3533, 2006-05-19)
DE2_firstProjectV1\DE2_TOP.map.eqn (53527, 2006-05-19)
... ...
DE2_Top
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This design is a bare-bones design containing all the pin assignments available on the DE2 board. It also contains a Verilog module with all the input/output ports corresponding to each pin. This can be used as a starting point for designs on the board.
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