VLSI-Project-Median-filer
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：14449KB
下载次数：71
上传日期：2013-06-27 10:37:55
上 传 者：
isenliu
说明： FPGA和ASIC实现的图像中值滤波模块，各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。
(FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the USTC VLSI design optimization final project. With the final version of the report and the presention.)
文件列表:
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\compare3.v (650, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\compare3.v.bak (1014, 2013-04-23)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\altsyncram_kga1.tdf (29054, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\altsyncram_pga1.tdf (29030, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\cmpr_ugc.tdf (2238, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\cntr_ksf.tdf (4231, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\logic_util_heursitic.dat (0, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(0).cnf.cdb (3283, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(0).cnf.hdb (1493, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(1).cnf.cdb (4565, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(1).cnf.hdb (2127, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(10).cnf.cdb (1332, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(10).cnf.hdb (571, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(11).cnf.cdb (1676, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(11).cnf.hdb (575, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(12).cnf.cdb (2613, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(12).cnf.hdb (895, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(2).cnf.cdb (1703, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(2).cnf.hdb (1095, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(3).cnf.cdb (1332, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(3).cnf.hdb (568, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(4).cnf.cdb (1676, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(4).cnf.hdb (582, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(5).cnf.cdb (2613, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(5).cnf.hdb (903, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(6).cnf.cdb (4378, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(6).cnf.hdb (1084, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(7).cnf.cdb (1101, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(7).cnf.hdb (711, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(8).cnf.cdb (5133, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(8).cnf.hdb (1990, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(9).cnf.cdb (4871, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.(9).cnf.hdb (1709, 2013-05-11)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.ace_cmp.bpm (843, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.ace_cmp.cdb (113245, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.ace_cmp.hdb (26678, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.ae.hdb (20368, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.amm.cdb (711, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.asm.qmsg (2250, 2013-06-07)
VLSI_Project_刘克辉_母志强\code\median_filter_FPGA\db\median_filter.asm.rdb (1368, 2013-06-07)
... ...
本文件夹包含三个子文件夹,其中:
1:median_filter_FPGA
图像中值滤波模块的FPGA实现,顶层模块是image_process,包括生成窗函数的window_3x3_ram模块,
中值滤波的median_filter模块。compare3是三输入比较器模块,也是关键路径所在的模块。
2: median_filter_ASIC
图像中值滤波模块的ASIC实现,顶层模块是image_process,包括生成窗函数的window_3x3_ram模块,
中值滤波的median_filter模块。compare3是三输入比较器模块,也是关键路径所在的模块。与FPGA
实现的差别在于line_buffer的生成,其他是一样的。报告中line_buffer我们是直接用寄存器组生成
的,比较耗资源。
3:simulation
各模块的modelsim仿真,包括图像中值滤波顶层模块,窗函数的生成,中值滤波。直接执行do文件即可。
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