divider_VERILOG
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：83KB
下载次数：8
上传日期：2013-07-09 21:23:12
上 传 者：
china_qiyong
说明： 采用VERILOG实现硬件除法器。提供RTL代码和仿真文件。
(Achieved using VERILOG hardware divider. Provide RTL code and simulation files.)
文件列表:
divider_VERILOG\bench\verilog\bench_div_top.v (5368, 2003-09-17)
divider_VERILOG\bench\verilog\timescale.v (23, 2002-10-31)
divider_VERILOG\rtl\verilog\bench_div_top.v (5368, 2003-09-17)
divider_VERILOG\rtl\verilog\div.v (5012, 2002-10-30)
divider_VERILOG\rtl\verilog\div_su.v (4460, 2002-10-31)
divider_VERILOG\rtl\verilog\div_us.v (3402, 2002-10-30)
divider_VERILOG\rtl\verilog\div_uu.v (5689, 2003-09-17)
divider_VERILOG\rtl\verilog\mydiv\bench_div_top_summary.html (3714, 2011-02-21)
divider_VERILOG\rtl\verilog\mydiv\div_su.cmd_log (144, 2011-02-21)
divider_VERILOG\rtl\verilog\mydiv\div_su.lso (6, 2011-02-21)
divider_VERILOG\rtl\verilog\mydiv\div_su.prj (56, 2011-02-21)
divider_VERILOG\rtl\verilog\mydiv\div_su.syr (4330, 2011-02-21)
divider_VERILOG\rtl\verilog\mydiv\div_su.xst (1216, 2011-02-21)
divider_VERILOG\rtl\verilog\mydiv\div_su_envsettings.html (9391, 2011-03-06)
divider_VERILOG\rtl\verilog\mydiv\div_su_summary.html (4082, 2011-03-06)
divider_VERILOG\rtl\verilog\mydiv\div_su_xst.xrpt (8795, 2011-02-21)
divider_VERILOG\rtl\verilog\mydiv\iseconfig\div_su.xreport (20845, 2011-03-06)
divider_VERILOG\rtl\verilog\mydiv\iseconfig\mydiv.projectmgr (5893, 2011-03-06)
divider_VERILOG\rtl\verilog\mydiv\mydiv.gise (4300, 2011-03-06)
divider_VERILOG\rtl\verilog\mydiv\mydiv.xise (36223, 2011-03-06)
divider_VERILOG\rtl\verilog\mydiv\webtalk_pn.xml (2666, 2011-02-21)
divider_VERILOG\rtl\verilog\mydiv\_xmsgs\pn_parser.xmsgs (2668, 2011-03-06)
divider_VERILOG\rtl\verilog\mydiv\_xmsgs\xst.xmsgs (569, 2011-02-21)
divider_VERILOG\rtl\verilog\timescale.v (23, 2002-10-31)
divider_VERILOG\rtl\verilog\work\bench_div_top\_primary.dat (2204, 2011-02-21)
divider_VERILOG\rtl\verilog\work\bench_div_top\_primary.dbs (6559, 2011-02-21)
divider_VERILOG\rtl\verilog\work\bench_div_top\_primary.vhd (226, 2011-02-21)
divider_VERILOG\rtl\verilog\work\div\_primary.dat (2227, 2011-02-21)
divider_VERILOG\rtl\verilog\work\div\_primary.dbs (6452, 2011-02-21)
divider_VERILOG\rtl\verilog\work\div\_primary.vhd (428, 2011-02-21)
divider_VERILOG\rtl\verilog\work\div_su\_primary.dat (1493, 2011-02-21)
divider_VERILOG\rtl\verilog\work\div_su\_primary.dbs (3854, 2011-02-21)
divider_VERILOG\rtl\verilog\work\div_su\_primary.vhd (520, 2011-02-21)
divider_VERILOG\rtl\verilog\work\div_uu\_primary.dat (2642, 2011-02-21)
divider_VERILOG\rtl\verilog\work\div_uu\_primary.dbs (8443, 2011-02-21)
divider_VERILOG\rtl\verilog\work\div_uu\_primary.vhd (520, 2011-02-21)
divider_VERILOG\rtl\verilog\work\_info (1004, 2011-02-21)
divider_VERILOG\rtl\verilog\work\_temp\vlog36q5ce (1000, 2011-02-21)
divider_VERILOG\rtl\verilog\work\_temp\vlog5cmmwx (4275, 2011-02-21)
divider_VERILOG\rtl\verilog\work\_temp\vlog5dndw5 (5026, 2011-02-21)
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