RS
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：26KB
下载次数：23
上传日期：2013-07-18 16:09:22
上 传 者：
liyongchao
说明： 通过verilog hdl语言实现RS编码器与译码器的设计
(Verilog hdl language through the RS encoder and decoder design)
文件列表:
RS编码器\mula_0.v (196, 2009-07-20)
RS编码器\mula_1.v (205, 2009-07-20)
RS编码器\mula_10.v (248, 2009-07-20)
RS编码器\mula_11.v (255, 2009-07-20)
RS编码器\mula_12.v (255, 2009-07-20)
RS编码器\mula_13.v (269, 2009-07-21)
RS编码器\mula_14.v (283, 2009-07-21)
RS编码器\mula_15.v (297, 2009-07-20)
RS编码器\mula_16.v (321, 2009-07-21)
RS编码器\mula_17.v (328, 2009-07-21)
RS编码器\mula_18.v (325, 2009-07-20)
RS编码器\mula_2.v (212, 2009-07-21)
RS编码器\mula_21.v (288, 2009-07-21)
RS编码器\mula_22.v (277, 2009-07-20)
RS编码器\mula_25.v (281, 2009-07-20)
RS编码器\mula_3.v (219, 2009-07-21)
RS编码器\mula_31.v (260, 2009-07-20)
RS编码器\mula_32.v (261, 2009-07-20)
RS编码器\mula_35.v (309, 2009-07-20)
RS编码器\mula_38.v (337, 2009-07-20)
RS编码器\mula_4.v (226, 2009-07-21)
RS编码器\mula_45.v (289, 2009-07-21)
RS编码器\mula_48.v (293, 2009-07-20)
RS编码器\mula_5.v (233, 2009-07-20)
RS编码器\mula_51.v (322, 2009-07-21)
RS编码器\mula_59.v (269, 2009-07-20)
RS编码器\mula_6.v (247, 2009-07-20)
RS编码器\mula_61.v (220, 2009-07-20)
RS编码器\mula_7.v (248, 2009-07-20)
RS编码器\mula_8.v (247, 2009-07-20)
RS编码器\mula_9.v (247, 2009-07-20)
RS编码器\mul_encode.vhd (3216, 2008-01-21)
RS编码器\rscode.v (2256, 2009-07-21)
RS编码器\rscode.vhd (7911, 2007-12-11)
RS编码器\rscode.vwf (8616, 2009-07-21)
RS编码器\rstestbench.vhd (1142, 2008-05-05)
RS编码器\testbenchmul.vhd (1245, 2007-12-08)
RS编码器\testbenchmul_encode.vhd (1273, 2008-01-21)
RS编码器 (0, 2013-01-27)
RS(204,188)译码器的设计\BM_KES.v (5102, 2006-07-02)
... ...
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