文件列表:

sdr_sdram_controller\sdr_sdram.pdf (645561, 2001-10-14)
sdr_sdram_controller\verilog\doc\sdr_sdram.pdf (645561, 2000-05-30)
sdr_sdram_controller\verilog\model\mt48lc8m16a2.v (43832, 2000-05-23)
sdr_sdram_controller\verilog\route\PLL1.v (4647, 2000-05-22)
sdr_sdram_controller\verilog\route\sdr_sdram.csf (3524, 2000-07-25)
sdr_sdram_controller\verilog\route\sdr_sdram.esf (471, 2000-07-25)
sdr_sdram_controller\verilog\route\sdr_sdram.vqm (164902, 2000-07-12)
sdr_sdram_controller\verilog\simulation\modelsim.ini (7728, 2000-05-19)
sdr_sdram_controller\verilog\simulation\sdr_sdram_tb.v (22444, 2000-07-12)
sdr_sdram_controller\verilog\simulation\work\altclklock\verilog.psm (20672, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\altclklock\_primary.dat (2337, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\altclklock\_primary.vhd (898, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\command\verilog.psm (47616, 2000-07-12)
sdr_sdram_controller\verilog\simulation\work\command\_primary.dat (5388, 2000-07-12)
sdr_sdram_controller\verilog\simulation\work\command\_primary.vhd (1319, 2000-07-12)
sdr_sdram_controller\verilog\simulation\work\control_interface\verilog.psm (21576, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\control_interface\_primary.dat (2751, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\control_interface\_primary.vhd (1105, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\mt48lc8m16a2\verilog.psm (240800, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\mt48lc8m16a2\_primary.dat (24807, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\mt48lc8m16a2\_primary.vhd (1291, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\pll1\verilog.psm (4872, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\pll1\_primary.dat (827, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\pll1\_primary.vhd (256, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\sdr_data_path\verilog.psm (5704, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\sdr_data_path\_primary.dat (984, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\sdr_data_path\_primary.vhd (607, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\sdr_sdram\verilog.psm (18064, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\sdr_sdram\_primary.dat (2893, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\sdr_sdram\_primary.vhd (1020, 2000-05-23)
sdr_sdram_controller\verilog\simulation\work\sdr_sdram_tb\verilog.psm (61256, 2000-07-12)
sdr_sdram_controller\verilog\simulation\work\sdr_sdram_tb\_primary.dat (9607, 2000-07-12)
sdr_sdram_controller\verilog\simulation\work\sdr_sdram_tb\_primary.vhd (102, 2000-07-12)
sdr_sdram_controller\verilog\simulation\work\_info (1247, 2000-07-12)
sdr_sdram_controller\verilog\source\altclklock.v (8543, 2000-06-12)
sdr_sdram_controller\verilog\source\Command.v (17328, 2000-07-28)
sdr_sdram_controller\verilog\source\compile_all.v (206, 2000-05-19)
sdr_sdram_controller\verilog\source\control_interface.v (8463, 2000-07-28)
... ...

SDR SDRAM Controller VHDL Reference Design version 1.1. This readme files describes the contents of each directory of the SDR SDRAM Controller reference design version 1.1. File/Directory Description ============================================================================= \doc SDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the vhdl testbench, modelsim project file, and library \source Contains the vhdl source files for the SDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design

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