CoreFIR_RTL-3.0
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1027KB
下载次数：30
上传日期：2013-08-06 15:34:11
上 传 者：
XYQ107815
说明： actelIP核 的fircore
Core Generator
– Executable File Outputs Run-Time Library (RTL)
Code and Testbench Based on Input Parameters
– Self-Checking – Executable Tests Generated
Output against Algorithm
• Distributed Arithmetic (DA) Algorithm
– Multiplier-Free Computation
– Low Cost
– Optimized for Actel FPGAs
• Folding Architecture to Minimize Design Size
– Serialized Computation when System Clock
Rate is Faster than the Data Sample Rate
• Efficient Structure Using Embedded RAMs
– Lookup Tables Utilize Embedded RAMs
• On-Chip DA Lookup Table Generator for FPGA
with Embedded RAMs
• Embedded RAMs Initialized as DA Lookup Table
• DA Lookup Table ROM Synthesis for FPGA without
Embedded RAMs
• Multiple DA lookup Tables to Split Large Number
of Taps
• Actel FPGA-Optimized RTL Code
• Supports 2 to 128 Taps
• 1- to 32-Bit Input Data and Coefficient Precision
(actelIPcore fircore
Core Generator
– Executable File Outputs Run-Time Library (RTL)
Code and Testbench Based on Input Parameters
– Self-Checking – Executable Tests Generated
Output against Algorithm
• Distributed Arithmetic (DA) Algorithm
– Multiplier-Free Computation
– Low Cost
– Optimized for Actel FPGAs
• Folding Architecture to Minimize Design Size
– Serialized Computation when System Clock
Rate is Faster than the Data Sample Rate
• Efficient Structure Using Embedded RAMs
– Lookup Tables Utilize Embedded RAMs
• On-Chip DA Lookup Table Generator for FPGA
with Embedded RAMs
• Embedded RAMs Initialized as DA Lookup Table
• DA Lookup Table ROM Synthesis for FPGA without
Embedded RAMs
• Multiple DA lookup Tables to Split Large Number
of Taps
• Actel FPGA-Optimized RTL Code
• Supports 2 to 128 Taps
• 1- to 32-Bit Input Data and Coefficient Precision)
文件列表:
release_3.0\actfirgen.exe (479232, 2005-01-19)
release_3.0\config.txt (110, 2006-03-07)
release_3.0\CoreFIR.exe (245842, 2006-03-06)
release_3.0\docs (0, 2006-06-06)
release_3.0\docs\CoreFIR_DS.pdf (206981, 2006-06-05)
release_3.0\docs\CoreFIR_QS.pdf (672338, 2006-06-05)
release_3.0\fir_const.srm (3029, 2006-02-28)
release_3.0\fir_const_pack.srm (1365, 2006-02-28)
release_3.0\fir_const_tap.srm (1609, 2006-02-28)
release_3.0\fir_const_tb.srm (13710, 2006-02-28)
release_3.0\sample_cfg.txt (221, 2005-01-19)
release_3.0\Config.exe (73728, 2006-06-07)
--------------------------------------
CoreFIR Generator Configuration Editor
Release: 1.0
Date: 06-06-06
--------------------------------------
Starting the editor
-------------------
To start the conifiguration editor, run the Config.exe file located in your CoreFIR Generator directory by double-clicking it in the windows explorer window
Editing and Saving
------------------
You may edit the following parameters via the editor:
- Module name
- Number of input data bits
- Number of coefficient data bits
- The data type (signed or unsigned)
- Taps
NOTE:
To remove existing taps from the list, use the "Remove Tap" button below the list. To add new taps, simply write in the desired value in the blank slot at the bottom of the list and hit the RETURN key.
To save the new configuration, select the "File->Verify and Save" button.
You may always revert to the last saved configuration by using the "File->Reset" option.
ANY ERROR MESSAGES WILL APPEAR IN THE STATUS BAR AT THE BOTTOM OF THE WINDOW
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