turbo[1].tar
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：83KB
下载次数：463
上传日期：2006-12-10 22:19:49
上 传 者：
liugu888
说明： turbo码的verilog程序，有意者请下载。
(turbo code verilog procedures Interested parties please download.)
文件列表:
. (0, 2005-06-14)
.\src (0, 2005-05-08)
.\src\myhdl (0, 2005-06-14)
.\src\myhdl\select.py (4370, 2005-06-14)
.\src\myhdl\acs.py (5308, 2005-06-14)
.\src\myhdl\limiter.py (4516, 2005-06-14)
.\src\myhdl\testbench.py (7159, 2005-06-14)
.\src\myhdl\distances.py (7162, 2005-06-14)
.\src\myhdl\trellis.py (15484, 2005-06-14)
.\src\myhdl\sova.py (5316, 2005-06-14)
.\src\myhdl\launchTurbo.py (7484, 2005-06-14)
.\src\myhdl\coder.py (4232, 2005-06-14)
.\src\myhdl\args.py (3222, 2005-06-14)
.\src\myhdl\permut.py (4115, 2005-06-14)
.\src\myhdl\misc.py (11134, 2005-06-14)
.\src\myhdl\noiser.py (5626, 2005-06-14)
.\src\myhdl\synthesis.py (191, 2005-06-14)
.\src\myhdl\turboTop.py (8763, 2005-06-14)
.\src\myhdl\punct.py (5561, 2005-06-14)
.\src\myhdl\clock.py (3874, 2005-06-14)
.\src\myhdl\iteration.py (8473, 2005-06-14)
.\src\myhdl\interleaver.py (7109, 2005-06-14)
.\src\myhdl\extInf.py (4925, 2005-06-14)
.\src\vhdl (0, 2005-06-14)
.\src\vhdl\trellis1_e.vhd (3679, 2005-06-14)
.\src\vhdl\subs_synth.vhd (2982, 2005-06-14)
.\src\vhdl\iteration_synth.vhd (13826, 2005-06-14)
.\src\vhdl\limiter_synth.vhd (4678, 2005-06-14)
.\src\vhdl\coder_synth.vhd (3292, 2005-06-14)
.\src\vhdl\extInf_synth.vhd (5263, 2005-06-14)
.\src\vhdl\extInf_e.vhd (3819, 2005-06-14)
.\src\vhdl\subs_e.vhd (3152, 2005-06-14)
.\src\vhdl\mux4_e.vhd (3326, 2005-06-14)
.\src\vhdl\mux8_e.vhd (3129, 2005-06-14)
.\src\vhdl\limiter_e.vhd (3998, 2005-06-14)
.\src\vhdl\reduction_synth.vhd (3247, 2005-06-14)
.\src\vhdl\sova_e.vhd (3870, 2005-06-14)
.\src\vhdl\stateSel_synth.vhd (3203, 2005-06-14)
.\src\vhdl\reg_e.vhd (3146, 2005-06-14)
.\src\vhdl\clkDiv_synth.vhd (3073, 2005-06-14)
... ...
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