UART-FPGA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：9697KB
下载次数：8
上传日期：2013-08-19 10:56:28
上 传 者：
DDSDDFSDFS
说明： verilog的UART通信，解决了接受过程中的毛刺问题，将接受和发送两个过程独立开来
(The UART verilog communication, solve problems receiving glitches during the process of receiving and sending two separate open)
文件列表:
UART-FPGA (0, 2013-08-18)
UART-FPGA\db (0, 2013-08-18)
UART-FPGA\db\altsyncram_2hq1.tdf (38300, 2013-07-26)
UART-FPGA\db\altsyncram_as14.tdf (3688, 2013-07-26)
UART-FPGA\db\altsyncram_gs14.tdf (3682, 2013-07-26)
UART-FPGA\db\altsyncram_igq1.tdf (39466, 2013-07-26)
UART-FPGA\db\altsyncram_is14.tdf (3692, 2013-07-26)
UART-FPGA\db\altsyncram_ogq1.tdf (32470, 2013-07-26)
UART-FPGA\db\altsyncram_qgq1.tdf (44130, 2013-07-26)
UART-FPGA\db\altsyncram_qs14.tdf (3687, 2013-07-26)
UART-FPGA\db\cmpr_5cc.tdf (1682, 2013-07-26)
UART-FPGA\db\cmpr_9cc.tdf (2004, 2013-07-26)
UART-FPGA\db\cmpr_acc.tdf (2074, 2013-07-26)
UART-FPGA\db\cntr_2ci.tdf (4002, 2013-07-26)
UART-FPGA\db\cntr_gui.tdf (3437, 2013-07-26)
UART-FPGA\db\cntr_qbi.tdf (4002, 2013-07-26)
UART-FPGA\db\cntr_sbi.tdf (4002, 2013-07-26)
UART-FPGA\db\cntr_tbi.tdf (4002, 2013-07-26)
UART-FPGA\db\cntr_u4j.tdf (4234, 2013-07-26)
UART-FPGA\db\cntr_vbi.tdf (4132, 2013-07-26)
UART-FPGA\db\decode_rqf.tdf (1563, 2013-07-26)
UART-FPGA\db\logic_util_heursitic.dat (69432, 2013-07-26)
UART-FPGA\db\mux_9oc.tdf (4723, 2013-07-26)
UART-FPGA\db\prev_cmp_UART.map.qmsg (9992, 2013-07-20)
UART-FPGA\db\prev_cmp_UART.qmsg (6282, 2013-07-26)
UART-FPGA\db\UART.db_info (154, 2013-08-18)
UART-FPGA\db\UART.ipinfo (252, 2013-08-18)
UART-FPGA\db\UART.sld_design_entry.sci (740, 2013-08-18)
UART-FPGA\greybox_tmp (0, 2013-08-18)
UART-FPGA\greybox_tmp\cbx_args.txt (1436, 2013-07-26)
UART-FPGA\incremental_db (0, 2013-08-18)
UART-FPGA\incremental_db\compiled_partitions (0, 2013-08-18)
UART-FPGA\incremental_db\compiled_partitions\UART.autoh_e4eb1.map.dpi (1414, 2013-07-26)
UART-FPGA\incremental_db\compiled_partitions\UART.autoh_e4eb1.map.kpt (2072, 2013-07-26)
UART-FPGA\incremental_db\compiled_partitions\UART.autoh_e4eb1.map.logdb (4, 2013-07-26)
UART-FPGA\incremental_db\compiled_partitions\UART.autos_3e921.map.dpi (8356, 2013-07-26)
UART-FPGA\incremental_db\compiled_partitions\UART.autos_3e921.map.kpt (18810, 2013-07-26)
UART-FPGA\incremental_db\compiled_partitions\UART.autos_3e921.map.logdb (4, 2013-07-26)
UART-FPGA\incremental_db\compiled_partitions\UART.db_info (154, 2013-08-12)
UART-FPGA\incremental_db\compiled_partitions\UART.root_partition.cmp.dfp (33, 2013-07-26)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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