文件列表:

IIC设计\i2c\i2c\bench\CVS\Entries (14, 2013-04-22)
IIC设计\i2c\i2c\bench\CVS\Repository (10, 2013-04-22)
IIC设计\i2c\i2c\bench\CVS\Root (13, 2013-04-22)
IIC设计\i2c\i2c\bench\verilog\CVS\Entries (200, 2013-04-22)
IIC设计\i2c\i2c\bench\verilog\CVS\Repository (18, 2013-04-22)
IIC设计\i2c\i2c\bench\verilog\CVS\Root (13, 2013-04-22)
IIC设计\i2c\i2c\bench\verilog\i2c_slave_model.v (11527, 2013-04-22)
IIC设计\i2c\i2c\bench\verilog\spi_slave_model.v (3934, 2013-04-22)
IIC设计\i2c\i2c\bench\verilog\tst_bench_top.v (14591, 2013-04-22)
IIC设计\i2c\i2c\bench\verilog\wb_master_model.v (5566, 2013-04-22)
IIC设计\i2c\i2c\CVS\Entries (102, 2013-04-22)
IIC设计\i2c\i2c\CVS\Repository (4, 2013-04-22)
IIC设计\i2c\i2c\CVS\Root (13, 2013-04-22)
IIC设计\i2c\i2c\doc\CVS\Entries (59, 2013-04-22)
IIC设计\i2c\i2c\doc\CVS\Repository (8, 2013-04-22)
IIC设计\i2c\i2c\doc\CVS\Root (13, 2013-04-22)
IIC设计\i2c\i2c\doc\i2c_specs.pdf (277959, 2013-04-22)
IIC设计\i2c\i2c\doc\src\CVS\Entries (51, 2013-04-22)
IIC设计\i2c\i2c\doc\src\CVS\Repository (12, 2013-04-22)
IIC设计\i2c\i2c\doc\src\CVS\Root (13, 2013-04-22)
IIC设计\i2c\i2c\doc\src\I2C_specs.doc (464896, 2013-04-22)
IIC设计\i2c\i2c\documentation\CVS\Entries (2, 2013-04-22)
IIC设计\i2c\i2c\documentation\CVS\Repository (18, 2013-04-22)
IIC设计\i2c\i2c\documentation\CVS\Root (13, 2013-04-22)
IIC设计\i2c\i2c\rtl\CVS\Entries (25, 2013-04-22)
IIC设计\i2c\i2c\rtl\CVS\Repository (8, 2013-04-22)
IIC设计\i2c\i2c\rtl\CVS\Root (13, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\CVS\Entries (259, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\CVS\Repository (16, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\CVS\Root (13, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\db\i2c_master_top.(0).cnf.cdb (9555, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\db\i2c_master_top.(0).cnf.hdb (1921, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\db\i2c_master_top.(1).cnf.cdb (9452, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\db\i2c_master_top.(1).cnf.hdb (1477, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\db\i2c_master_top.(2).cnf.cdb (9503, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\db\i2c_master_top.(2).cnf.hdb (2187, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\db\i2c_master_top.asm.qmsg (2153, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\db\i2c_master_top.asm_labs.ddb (130422, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\db\i2c_master_top.cbx.xml (96, 2013-04-22)
IIC设计\i2c\i2c\rtl\verilog\db\i2c_master_top.cmp.bpm (758, 2013-04-22)
... ...

-- This code is provided for free and may be used and -- -- distributed without restriction provided that the -- -- copyright statement is not removed from the file and -- -- that any derivative work contains the original -- -- copyright notice and the associated disclaimer. -- -- Comments and suggestions are always welcome -- The i2c_master core consists of three files: - i2c_master_top -- top level - i2c_master_byte_ctrl -- byte controller - i2c_master_bit_ctrl -- bit controller VHDL needs to be compiled in order. The files are listed above in descending order. I2C.VHD and tst_ds1621.vhd are not supported anymore. They remain mostly for historical purposes, altough they might prove usefull. Richard Herveille rherveille@opencores.org

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