ddr2
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：8106KB
下载次数：200
上传日期：2013-08-31 00:37:54
上 传 者：
yoeksome
说明： xilinx ddr2 mig核读写控制 verilog
(xilinx mig write and read timing)
文件列表:
ddr2\ddr2.gise (1245, 2013-07-25)
ddr2\ddr2.xise (35829, 2013-07-25)
ddr2\ipcore_dir\coregen.cgp (238, 2013-07-17)
ddr2\ipcore_dir\coregen.log (1246, 2013-07-17)
ddr2\ipcore_dir\create_ddr2.tcl (1272, 2013-07-17)
ddr2\ipcore_dir\ddr2\docs\ug388.pdf (2172724, 2010-10-06)
ddr2\ipcore_dir\ddr2\docs\ug416.pdf (7337767, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\datasheet.txt (2358, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\log.txt (2562, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\mig.prj (2957, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\create_ise.bat (3142, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\example_top.ucf (9886, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\icon_coregen.xco (1382, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\ila_coregen.xco (3871, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\ise_flow.bat (3930, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\ise_run.txt (1278, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\makeproj.bat (28, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\mem_interface_top.ut (385, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\rem_files.bat (7956, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\set_ise_prop.tcl (5879, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\par\vio_coregen.xco (1570, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\rtl\example_top.v (55341, 2013-07-17)
ddr2\ipcore_dir\ddr2\example_design\rtl\infrastructure.v (10438, 2010-12-01)
ddr2\ipcore_dir\ddr2\example_design\rtl\mcb_controller\iodrp_controller.v (11430, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\mcb_controller\iodrp_mcb_controller.v (15423, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\mcb_controller\mcb_raw_wrapper.v (265405, 2010-12-05)
ddr2\ipcore_dir\ddr2\example_design\rtl\mcb_controller\mcb_soft_calibration.v (57123, 2010-10-22)
ddr2\ipcore_dir\ddr2\example_design\rtl\mcb_controller\mcb_soft_calibration_top.v (12394, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\mcb_controller\mcb_ui_top.v (113866, 2010-12-08)
ddr2\ipcore_dir\ddr2\example_design\rtl\memc_tb_top.v (86783, 2010-12-25)
ddr2\ipcore_dir\ddr2\example_design\rtl\memc_wrapper.v (66098, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\traffic_gen\afifo.v (6916, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\traffic_gen\cmd_gen.v (31157, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\traffic_gen\cmd_prbs_gen.v (10179, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\traffic_gen\data_prbs_gen.v (4609, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\traffic_gen\init_mem_pattern_ctr.v (23533, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\traffic_gen\mcb_flow_control.v (17386, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\traffic_gen\mcb_traffic_gen.v (26129, 2010-10-06)
ddr2\ipcore_dir\ddr2\example_design\rtl\traffic_gen\rd_data_gen.v (11019, 2010-10-06)
... ...
The design files are located at
E:/work/ddr2/ddr2_8/ddr2/ipcore_dir:
- ddr2.veo:
veo template file containing code that can be used as a model
for instantiating a CORE Generator module in a HDL design.
- ddr2.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
- ddr2_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
- ddr2_readme.txt:
Text file indicating the files generated and how they are used.
- ddr2_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
- ddr2 directory.
In the ddr2 directory, three folders are created:
- docs:
This folder contains user guide.
- example_design:
This folder includes the design with synthesizable test bench.
- user_design:
This folder includes the design without test bench modules.
The example_design and user_design folders contain several other folders
and files. All these output folders are discussed in more detail in
Spartan-6 FPGA Memory Controller user guide (ug388.pdf) located in docs folder.
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