WISHBONE_conmax
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：651KB
下载次数：4
上传日期：2013-09-03 11:11:05
上 传 者：
haizi849738301
说明： 很详细的wishbone总线学习借鉴代码和文档
(Very detailed wishbone bus to learn from the code and documentation)
文件列表:
WISHBONE_conmax (0, 2012-11-14)
WISHBONE_conmax\branches (0, 2013-09-03)
WISHBONE_conmax\tags (0, 2012-11-14)
WISHBONE_conmax\tags\start (0, 2012-11-14)
WISHBONE_conmax\tags\start\bench (0, 2012-11-14)
WISHBONE_conmax\tags\start\bench\verilog (0, 2012-11-14)
WISHBONE_conmax\tags\start\bench\verilog\test_bench_top.v (23230, 2001-10-19)
WISHBONE_conmax\tags\start\bench\verilog\tests.v (21599, 2001-10-19)
WISHBONE_conmax\tags\start\bench\verilog\wb_mast_model.v (10455, 2001-10-19)
WISHBONE_conmax\tags\start\bench\verilog\wb_model_defines.v (2690, 2001-10-19)
WISHBONE_conmax\tags\start\bench\verilog\wb_slv_model.v (4956, 2001-10-19)
WISHBONE_conmax\tags\start\doc (0, 2012-11-14)
WISHBONE_conmax\tags\start\doc\STATUS.txt (538, 2001-10-19)
WISHBONE_conmax\tags\start\doc\conmax.pdf (83521, 2001-10-19)
WISHBONE_conmax\tags\start\mast1.pl (1507, 2001-10-19)
WISHBONE_conmax\tags\start\rtl (0, 2012-11-14)
WISHBONE_conmax\tags\start\rtl\verilog (0, 2012-11-14)
WISHBONE_conmax\tags\start\rtl\verilog\wb_conmax_arb.v (7495, 2001-10-19)
WISHBONE_conmax\tags\start\rtl\verilog\wb_conmax_defines.v (2835, 2001-10-19)
WISHBONE_conmax\tags\start\rtl\verilog\wb_conmax_master_if.v (17565, 2001-10-19)
WISHBONE_conmax\tags\start\rtl\verilog\wb_conmax_msel.v (7275, 2001-10-19)
WISHBONE_conmax\tags\start\rtl\verilog\wb_conmax_pri_dec.v (3960, 2001-10-19)
WISHBONE_conmax\tags\start\rtl\verilog\wb_conmax_pri_enc.v (5226, 2001-10-19)
WISHBONE_conmax\tags\start\rtl\verilog\wb_conmax_rf.v (9594, 2001-10-19)
WISHBONE_conmax\tags\start\rtl\verilog\wb_conmax_slave_if.v (12530, 2001-10-19)
WISHBONE_conmax\tags\start\rtl\verilog\wb_conmax_top.v (117982, 2001-10-19)
WISHBONE_conmax\tags\start\sim (0, 2012-11-14)
WISHBONE_conmax\tags\start\sim\rtl_sim (0, 2012-11-14)
WISHBONE_conmax\tags\start\sim\rtl_sim\bin (0, 2012-11-14)
WISHBONE_conmax\tags\start\sim\rtl_sim\bin\Makefile (3775, 2001-10-19)
WISHBONE_conmax\tags\start\sim\rtl_sim\run (0, 2012-11-14)
WISHBONE_conmax\tags\start\sim\rtl_sim\run\.nclog (26375, 2001-10-19)
WISHBONE_conmax\tags\start\sim\rtl_sim\run\ncwork (0, 2012-11-14)
WISHBONE_conmax\tags\start\sim\rtl_sim\run\ncwork\.cdsvmod (0, 2001-10-19)
WISHBONE_conmax\tags\start\sim\rtl_sim\run\ncwork\.inca.db.134.linux (0, 2001-10-19)
WISHBONE_conmax\tags\start\sim\rtl_sim\run\ncwork\cds.lib (23, 2001-10-19)
WISHBONE_conmax\tags\start\sim\rtl_sim\run\ncwork\hdl.var (1099, 2001-10-19)
WISHBONE_conmax\tags\start\sim\rtl_sim\run\ncwork\inca.linux.134.pak (2284693, 2001-10-19)
WISHBONE_conmax\tags\start\sim\rtl_sim\run\waves (0, 2012-11-14)
... ...
The WISHBONE CONMAX Project Page is:
http://www.opencores.org/cores/wb_conmax/
To find out more about me (Rudolf Usselmann), please visit:
http://www.asics.ws
Directory Structure
-------------------
[core_root]
|
+-doc Documentation
|
+-bench--+ Test Bench
| +- verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-rtl----+ Core RTL Sources
| +-verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-sim----+
| +-rtl_sim---+ Functional verification Directory
| | +-bin Makefiles/Run Scripts
| | +-run Working Directory
| |
| +-gate_sim--+ Functional & Timing Gate Level
| | Verification Directory
| +-bin Makefiles/Run Scripts
| +-run Working Directory
|
+-lint--+ Lint Directory Tree
| +-bin Makefiles/Run Scripts
| +-run Working Directory
| +-log Linter log & result files
|
+-syn---+ Synthesis Directory Tree
| +-bin Synthesis Scripts
| +-run Working Directory
| +-log Synthesis log files
| +-out Synthesis Output
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