Tri-mode_Ethernet_MAC
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1131KB
下载次数：106
上传日期：2013-09-04 16:46:55
上 传 者：
alpha1027
说明： 此包为三态以太网控制IP核，包内包含了仿真环境，说明文档，综合结果等文件。
(This package is tri-mode Ethernet Controller IP core, the package contains a simulation environment, documentation, comprehensive results and other documents.)
文件列表:
bench (0, 2013-09-04)
bench\verilog (0, 2013-09-04)
bench\verilog\altera_mf.v (1337985, 2009-05-25)
bench\verilog\host_sim.v (1706, 2009-05-25)
bench\verilog\Phy_sim.v (4414, 2009-05-25)
bench\verilog\reg_int_sim.v (6326, 2009-05-25)
bench\verilog\tb_top.v (9655, 2009-05-25)
bench\verilog\User_int_sim.v (5496, 2009-05-25)
doc (0, 2013-09-04)
doc\Tri-mode_Ethernet_MAC_Specifications.pdf (313150, 2009-05-25)
doc\Tri-mode_Ethernet_MAC_Verification_plan.pdf (144899, 2009-05-25)
EDK (0, 2013-09-04)
EDK\edk_user_repository.tar.gz (382513, 2009-05-25)
rtl (0, 2013-09-04)
rtl\verilog (0, 2013-09-04)
rtl\verilog\afifo.v (6425, 2009-05-25)
rtl\verilog\Clk_ctrl.v (5246, 2009-05-25)
rtl\verilog\eth_miim.v (16634, 2009-05-25)
rtl\verilog\header.v (190, 2009-05-25)
rtl\verilog\MAC_rx (0, 2013-09-04)
rtl\verilog\MAC_rx\Broadcast_filter.v (5144, 2009-05-25)
rtl\verilog\MAC_rx\CRC_chk.v (6212, 2009-05-25)
rtl\verilog\MAC_rx\MAC_rx_add_chk.v (6743, 2009-05-25)
rtl\verilog\MAC_rx\MAC_rx_ctrl.v (22304, 2009-05-25)
rtl\verilog\MAC_rx\MAC_rx_FF.v (26032, 2009-05-25)
rtl\verilog\MAC_rx.v (12124, 2009-05-25)
rtl\verilog\MAC_top.v (22795, 2009-05-25)
rtl\verilog\MAC_tx (0, 2013-09-04)
rtl\verilog\MAC_tx\CRC_gen.v (7274, 2009-05-25)
rtl\verilog\MAC_tx\flow_ctrl.v (7767, 2009-05-25)
rtl\verilog\MAC_tx\MAC_tx_addr_add.v (5860, 2009-05-25)
rtl\verilog\MAC_tx\MAC_tx_Ctrl.v (22985, 2009-05-25)
rtl\verilog\MAC_tx\MAC_tx_FF.v (26442, 2009-05-25)
rtl\verilog\MAC_tx\Ramdon_gen.v (5537, 2009-05-25)
rtl\verilog\MAC_tx.v (13101, 2009-05-25)
rtl\verilog\miim (0, 2013-09-04)
rtl\verilog\miim\eth_clockgen.v (5603, 2009-05-25)
rtl\verilog\miim\eth_outputcontrol.v (6412, 2009-05-25)
rtl\verilog\miim\eth_shiftreg.v (6843, 2009-05-25)
rtl\verilog\miim\timescale.v (3153, 2009-05-25)
... ...
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