dvi-code-verilog
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:155KB
下载次数:40
上传日期:2013-09-10 14:12:57
上 传 者:
iyoyoo
说明: dvi encoder and decoder for fpga
文件列表:
dvi code verilog\model\CY7C1338G_FT.v (17623, 2008-06-09)
dvi code verilog\model\CY7C1338G_FT_.v (17623, 2008-06-09)
dvi code verilog\model\dvi_patten_gen.v (1900, 2008-12-17)
dvi code verilog\model\mcu_stimulus.vhd (18917, 2008-12-11)
dvi code verilog\model\patten_gen.v (11309, 2008-11-19)
dvi code verilog\model\patten_gen_with_btn.v (14570, 2008-12-17)
dvi code verilog\model\patten_sel.v (1251, 2008-11-25)
dvi code verilog\model\swap_ctrl.v (1070, 2008-11-25)
dvi code verilog\model\vga2.vhd (3320, 2008-11-26)
dvi code verilog\model\VGA_Controller.v (3887, 2008-11-18)
dvi code verilog\model\VGA_Param.h (489, 2006-06-02)
dvi code verilog\model\vssver.scc (128, 2008-12-16)
dvi code verilog\rtl\clk_ctrl.v (4627, 2008-12-17)
dvi code verilog\rtl\common\debnce.v (3700, 2008-07-24)
dvi code verilog\rtl\common\hdclrbar.v (17508, 2008-07-24)
dvi code verilog\rtl\common\synchro.v (3890, 2008-07-24)
dvi code verilog\rtl\common\timing.v (8425, 2008-07-24)
dvi code verilog\rtl\common\vssver.scc (112, 2008-12-16)
dvi code verilog\rtl\core_gen\coregen.cgp (542, 2008-12-08)
dvi code verilog\rtl\core_gen\vssver.scc (272, 2008-12-16)
dvi code verilog\rtl\ctrl_main.ucf (10151, 2009-02-04)
dvi code verilog\rtl\ctrl_main.v (8004, 2009-02-10)
dvi code verilog\rtl\dvi_ctrl.v (1050, 2008-12-12)
dvi code verilog\rtl\dvi_ip\chnlbond.v (6161, 2009-02-06)
dvi code verilog\rtl\dvi_ip\core\dvi_tx_fifo.coe (8914, 2008-12-09)
dvi code verilog\rtl\dvi_ip\core\dvi_tx_fifo.mif (27234, 2008-12-09)
dvi code verilog\rtl\dvi_ip\core\dvi_tx_fifo.ngc (36576, 2008-12-09)
dvi code verilog\rtl\dvi_ip\core\dvi_tx_fifo.v (4545, 2008-12-09)
dvi code verilog\rtl\dvi_ip\core\dvi_tx_fifo.veo (3123, 2008-12-09)
dvi code verilog\rtl\dvi_ip\core\dvi_tx_fifo.xco (2292, 2008-12-09)
dvi code verilog\rtl\dvi_ip\core\dvi_tx_fifo_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt (2653, 2008-12-09)
dvi code verilog\rtl\dvi_ip\core\dvi_tx_fifo_flist.txt (219, 2008-12-09)
dvi code verilog\rtl\dvi_ip\core\dvi_tx_fifo_xmdf.tcl (2762, 2008-12-09)
dvi code verilog\rtl\dvi_ip\core\inputbuffer.ngc (33916, 2009-01-08)
dvi code verilog\rtl\dvi_ip\core\inputbuffer.vhd (5256, 2009-01-08)
dvi code verilog\rtl\dvi_ip\core\inputbuffer.vho (3520, 2009-01-08)
dvi code verilog\rtl\dvi_ip\core\inputbuffer.xco (2256, 2009-01-08)
dvi code verilog\rtl\dvi_ip\core\inputbuffer_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt (3496, 2009-01-08)
dvi code verilog\rtl\dvi_ip\core\inputbuffer_flist.txt (204, 2009-01-08)
... ...
The following files were generated for 'inputbuffer' in directory
D:\new_platform\firmware\aa.05\source\coregen\:
inputbuffer.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
inputbuffer.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
inputbuffer.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
inputbuffer.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
inputbuffer_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt:
Please see the core data sheet.
inputbuffer_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
inputbuffer_readme.txt:
Text file indicating the files generated and how they are used.
inputbuffer_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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