fir_test
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1009KB
下载次数：7
上传日期：2013-09-14 21:07:53
上 传 者：
3876230
说明： 采用xilinx进行的FPGA的FIR滤波器设计
(Conducted using xilinx FPGA FIR filter design)
文件列表:
fir_test (0, 2013-08-25)
fir_test\AD_control.vhd (1850, 2013-08-17)
fir_test\DA_control.vhd (1640, 2013-08-17)
fir_test\_ngo (0, 2013-08-25)
fir_test\_ngo\cs_icon_pro (0, 2013-08-24)
fir_test\_ngo\cs_icon_pro\_xmsgs (0, 2013-08-24)
fir_test\_ngo\cs_icon_pro\_xmsgs\xst.xmsgs (26404, 2013-08-17)
fir_test\_ngo\cs_icon_pro\coregen.cgc (16250, 2013-08-17)
fir_test\_ngo\cs_icon_pro\coregen.cgp (520, 2013-08-17)
fir_test\_ngo\cs_icon_pro\coregen.log (2307, 2013-08-17)
fir_test\_ngo\cs_icon_pro\generate_icon_pro.xco (684, 2013-08-17)
fir_test\_ngo\cs_icon_pro\icon_pro.gise (1167, 2013-08-17)
fir_test\_ngo\cs_icon_pro\icon_pro.ucf (375, 2013-08-17)
fir_test\_ngo\cs_icon_pro\icon_pro.vhd (947, 2013-08-17)
fir_test\_ngo\cs_icon_pro\icon_pro.vho (1366, 2013-08-17)
fir_test\_ngo\cs_icon_pro\icon_pro.xco (1660, 2013-08-17)
fir_test\_ngo\cs_icon_pro\icon_pro.xise (41252, 2013-08-17)
fir_test\_ngo\cs_icon_pro\icon_pro_flist.txt (199, 2013-08-17)
fir_test\_ngo\cs_icon_pro\icon_pro_xmdf.tcl (2504, 2013-08-17)
fir_test\_ngo\cs_icon_pro\tmp (0, 2013-08-24)
fir_test\_ngo\cs_icon_pro\tmp\_cg (0, 2013-09-14)
fir_test\_ngo\cs_icon_pro\tmp\_xmsgs (0, 2013-08-24)
fir_test\_ngo\cs_icon_pro\tmp\_xmsgs\pn_parser.xmsgs (776, 2013-08-17)
fir_test\_ngo\cs_ila_pro_0 (0, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\_xmsgs (0, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\_xmsgs\xst.xmsgs (31552, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\coregen.cgc (43910, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\coregen.cgp (520, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\coregen.log (2331, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\generate_ila_pro_0.xco (3184, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\ila_pro_0.cdc (3564, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\ila_pro_0.gise (1169, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\ila_pro_0.ucf (424, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\ila_pro_0.vhd (1022, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\ila_pro_0.vho (1475, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\ila_pro_0.xco (4221, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\ila_pro_0.xise (41267, 2013-08-24)
fir_test\_ngo\cs_ila_pro_0\ila_pro_0_flist.txt (225, 2013-08-24)
... ...
The following files were generated for 'fir' in directory
E:\EDC2013\fpga\dac904_test\ipcore_dir\
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* fir.mif
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* fir.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* fir.ngc
* fir.vhd
* fir.vho
* firCOEFF_auto0_0.mif
* firfilt_decode_rom.mif
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* fir.vho
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* fir.asy
* fir.mif
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* fir.sym
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* fir_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* fir.gise
* fir.xise
Deliver Readme:
Readme file for the IP.
* fir_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* fir_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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