QPSK_DSSS
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：6820KB
下载次数：69
上传日期：2013-09-18 15:31:17
上 传 者：
senjingjia
说明： 该程序使用verilog语言，编写了QPSK-DSSS系统的发端，主要模块包括对同相分量和正交分量的扩频，通过根升余弦滤波器，以及与载波相乘等模块。
(The program uses the verilog language, written QPSK-DSSS system, the originator, the main modules include in-phase and quadrature components of the spectrum, through the root raised cosine filter, as well as with carrier multiplication modules.)
文件列表:
QPSK_DSSS\fir.bmm (0, 2013-08-07)
QPSK_DSSS\fir.mif (1746, 2013-08-07)
QPSK_DSSS\firCOEFF_auto0_0.mif (306, 2013-08-07)
QPSK_DSSS\firCOEFF_auto0_1.mif (306, 2013-08-07)
QPSK_DSSS\firCOEFF_auto0_2.mif (306, 2013-08-07)
QPSK_DSSS\firCOEFF_auto0_3.mif (306, 2013-08-07)
QPSK_DSSS\firCOEFF_auto0_4.mif (306, 2013-08-07)
QPSK_DSSS\firCOEFF_auto0_5.mif (306, 2013-08-07)
QPSK_DSSS\firCOEFF_auto0_6.mif (306, 2013-08-07)
QPSK_DSSS\firfilt_decode_rom.mif (102, 2013-08-07)
QPSK_DSSS\ipcore_dir\.lso (19, 2013-08-07)
QPSK_DSSS\ipcore_dir\add\doc\c_addsub_v11_0_vinfo.html (6181, 2013-08-08)
QPSK_DSSS\ipcore_dir\add\doc\ds214_addsub.pdf (317089, 2013-08-08)
QPSK_DSSS\ipcore_dir\add.asy (424, 2013-08-08)
QPSK_DSSS\ipcore_dir\add.gise (1344, 2013-09-12)
QPSK_DSSS\ipcore_dir\add.ncf (0, 2013-09-08)
QPSK_DSSS\ipcore_dir\add.ngc (19362, 2013-08-08)
QPSK_DSSS\ipcore_dir\add.sym (1275, 2013-08-08)
QPSK_DSSS\ipcore_dir\add.v (19517, 2013-08-08)
QPSK_DSSS\ipcore_dir\add.veo (3901, 2013-08-08)
QPSK_DSSS\ipcore_dir\add.xco (2002, 2013-08-08)
QPSK_DSSS\ipcore_dir\add.xise (4978, 2013-08-08)
QPSK_DSSS\ipcore_dir\add_flist.txt (255, 2013-08-08)
QPSK_DSSS\ipcore_dir\add_xmdf.tcl (3148, 2013-08-08)
QPSK_DSSS\ipcore_dir\coregen.cgp (239, 2013-09-10)
QPSK_DSSS\ipcore_dir\coregen.log (316, 2013-09-10)
QPSK_DSSS\ipcore_dir\create_add.tcl (1260, 2013-08-08)
QPSK_DSSS\ipcore_dir\create_DDS.tcl (1258, 2013-08-08)
QPSK_DSSS\ipcore_dir\create_dds1.tcl (1259, 2013-09-10)
QPSK_DSSS\ipcore_dir\create_DDS_new.tcl (1262, 2013-08-08)
QPSK_DSSS\ipcore_dir\create_DDS_sin.tcl (1262, 2013-08-08)
QPSK_DSSS\ipcore_dir\create_dds_test.tcl (1263, 2013-09-10)
QPSK_DSSS\ipcore_dir\create_fir.tcl (1258, 2013-08-07)
QPSK_DSSS\ipcore_dir\create_hy.tcl (1257, 2013-08-07)
QPSK_DSSS\ipcore_dir\create_multiply.tcl (1253, 2013-08-08)
QPSK_DSSS\ipcore_dir\create_qq.tcl (1257, 2013-09-10)
QPSK_DSSS\ipcore_dir\create_rcosfir.tcl (1262, 2013-08-07)
QPSK_DSSS\ipcore_dir\create_ROM_I.tcl (1278, 2013-08-07)
QPSK_DSSS\ipcore_dir\create_ROM_PN.tcl (1279, 2013-08-07)
... ...
The following files were generated for 'DDS' in directory
D:\ISE_project\QPSK_DSSS\ipcore_dir\
Generate XCO file:
CORE Generator input file containing the parameters used to generate a core.
* DDS.xco
Generate Implementation Netlist:
Binary Xilinx implementation netlist files containing the information
required to implement the module in a Xilinx (R) FPGA.
* DDS.ngc
Obfuscate Netlist Generator:
Please see the core data sheet.
* DDS.ngc
Generate Instantiation Templates:
Template files containing code that can be used as a model for instantiating
a CORE Generator module in an HDL design.
* DDS.veo
RTL Simulation Model Generator:
Please see the core data sheet.
* DDS.v
All Documents Generator:
Please see the core data sheet.
* DDS/doc/dds_compiler_v4_0_vinfo.html
* DDS/doc/dds_ds558.pdf
Deliver IP Symbol:
Graphical symbol information file. Used by the ISE tools and some third party
tools to create a symbol representing the core.
* DDS.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* DDS.sym
Generate XMDF file:
ISE Project Navigator interface file. ISE uses this file to determine how the
files output by CORE Generator for the core can be integrated into your ISE
project.
* DDS_xmdf.tcl
Generate ISE project file:
ISE Project Navigator support files. These are generated files and should not
be edited directly.
* DDS.gise
* DDS.xise
* _xmsgs/pn_parser.xmsgs
Deliver Readme:
Readme file for the IP.
* DDS_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* DDS_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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