DTC_SCI_CRC
所属分类：单片机开发
开发工具：C/C++
文件大小：236KB
下载次数：16
上传日期：2013-09-18 18:54:47
上 传 者：
szlaowei
说明： 瑞萨单片机通过SCI接口实现的双CPU之间DMA通信，具有CRC校验，在实际项目中能够成功应用。
(Renesas microcontroller through the SCI interface dual-CPU communication between the DMA with CRC, the actual project can be successfully applied.)
文件列表:
DTC_SCI_CRC (0, 2013-09-18)
DTC_SCI_CRC\rx_dtc (0, 2013-09-18)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR (0, 2013-08-03)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR (0, 2013-08-03)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR.c (1231, 2010-11-26)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR.hwp (21959, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR.nav (29396, 2013-08-03)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR.tps (2051, 2013-08-03)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug (0, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\DTC_SCI_CRC_SR.abs (27540, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\DTC_SCI_CRC_SR.hlk (1308, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\DTC_SCI_CRC_SR.lbk (349418, 2010-11-26)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\DTC_SCI_CRC_SR.lib (360222, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\DTC_SCI_CRC_SR.map (3250, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\DTC_SCI_CRC_SR.mot (7002, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\DTC_SCI_CRC_SR.rxg (168, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\Debug.hdp (5537, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\dbsct.obj (5160, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\dbsct.rxc (228, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\intprg.obj (28426, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\intprg.rxc (230, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\main.obj (12546, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\main.rxc (226, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\resetprg.obj (3612, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\resetprg.rxc (234, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\sbrk.obj (3949, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\sbrk.rxc (226, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\vecttbl.obj (2712, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug\vecttbl.rxc (232, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug_RX600_E1_E20_SYSTEM (0, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Debug_RX600_E1_E20_SYSTEM\Debug_RX600_E1_E20_SYSTEM.hdp (807, 2013-08-03)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\DefaultSession.hsf (4196, 2010-11-26)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Release (0, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\Release\Release.hdp (771, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\SessionRX600_E1_E20_SYSTEM.hsf (16699, 2013-08-03)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\SessionRX600_E1_E20_SYSTEM.ini (616, 2010-12-09)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\SimDebug_RX600 (0, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\SimDebug_RX600\SimDebug_RX600.hdp (785, 2013-07-27)
DTC_SCI_CRC\rx_dtc\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\SimSessionRX600.hsf (2187, 2010-11-26)
... ...
-------- PROJECT GENERATOR --------
PROJECT NAME : DTC_SCI_CRC_SR
PROJECT DIRECTORY : C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR
CPU SERIES : RX600
CPU TYPE : RX62T
TOOLCHAIN NAME : Renesas RX Standard Toolchain
TOOLCHAIN VERSION : 1.0.1.0
GENERATION FILES :
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\dbsct.c
Setting of B,R Section
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\typedefine.h
Aliases of Integer Type
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\sbrk.c
Program of sbrk
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\iodefine.h
Definition of I/O Register
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\intprg.c
Interrupt Program
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\vecttbl.c
Initialize of Vector Table
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\vect.h
Definition of Vector
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\resetprg.c
Reset Program
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR.c
Main Program
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\sbrk.h
Header file of sbrk file
C:\Apn\workspace\DTC_SCI_CRC_SR\DTC_SCI_CRC_SR\stacksct.h
Setting of Stack area
START ADDRESS OF SECTION :
H'1000 B_1,R_1,B_2,R_2,B,R,SU,SI
H'FFFF8000 PResetPRG
H'FFFF8100 C_1,C_2,C,C$*,D*,P,PIntPRG,W*
H'FFFFFFD0 FIXEDVECT
* When the user program is executed,
* the interrupt mask has been masked.
*
* Program start 0xFFFF8000.
* RAM start 0x1000.
SELECT TARGET :
RX600 E1/E20 SYSTEM
RX600 Simulator
DATE & TIME : 2010/11/26 10:44:30
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