Flash_TimConst_AN
所属分类:单片机开发
开发工具:VHDL
文件大小:212KB
下载次数:1
上传日期:2013-09-25 10:06:55
上 传 者:
awublack
说明: Timing constraints are used to generate guidelines for synthesis and place-and-route tools to meet the
required timing performance for a design. In the current version of Designer, the timing-driven flow for
Flash devices is different than the flow for Antifuse families. In the Flash design flow, Timer does not
forward the constraints set in Timer to Layout. Usually, timing constraints set in Timer are saved in the
Design Constraint System (DCS) using the SDC format. For Flash devices, the timing-driven place-and-route
requires you to apply the constraints in GCF format. Therefore, any constraints set in Timer must be
converted to GCF format to be recognized by the place-and-route tool, and not all constraints set in the
Timer GUI can be converted to an equivalent GCF format. The following sections describe the Flash timing
constraints flow and how the user should use the Timer tool to set timing constraints for these families.
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Flash_TimConst_AN.pdf (234499, 2013-09-24)
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