fpga_ver
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：7871KB
下载次数：21
上传日期：2013-09-27 17:22:03
上 传 者：
lcyg1211
说明： Altera StratixII FPGA与DSP TS201实现总线通信的程序，Verilog实现
(Altera StratixII FPGA and DSP TS201 implement the bus communication procedures, Verilog realization)
文件列表:
fpga_ver\altpll_bus.cmp (970, 2012-06-29)
fpga_ver\altpll_bus.inc (872, 2012-06-29)
fpga_ver\altpll_bus.ppf (488, 2012-06-29)
fpga_ver\altpll_bus.qip (641, 2012-06-29)
fpga_ver\altpll_bus.v (16926, 2012-06-29)
fpga_ver\altpll_bus.v.bak (18269, 2012-06-28)
fpga_ver\altpll_bus_bb.v (12728, 2012-06-29)
fpga_ver\altpll_bus_inst.v (122, 2012-06-29)
fpga_ver\altpll_bus_wave0.jpg (402631, 2012-06-29)
fpga_ver\altpll_bus_waveforms.html (803, 2012-06-29)
fpga_ver\clear_jitter.v (1085, 2012-06-28)
fpga_ver\clear_jitter.v.bak (1085, 2012-06-28)
fpga_ver\db\altsyncram_16p3.tdf (169366, 2012-06-29)
fpga_ver\db\altsyncram_5q61.tdf (37938, 2012-06-29)
fpga_ver\db\altsyncram_73p3.tdf (93405, 2012-06-28)
fpga_ver\db\altsyncram_7ou.tdf (37779, 2012-06-28)
fpga_ver\db\altsyncram_93p3.tdf (94497, 2012-06-29)
fpga_ver\db\altsyncram_d3p3.tdf (86853, 2012-06-28)
fpga_ver\db\altsyncram_dn71.tdf (24190, 2012-06-29)
fpga_ver\db\altsyncram_h3p3.tdf (89037, 2012-06-28)
fpga_ver\db\altsyncram_hk71.tdf (24372, 2012-06-28)
fpga_ver\db\alt_synch_pipe_8u7.tdf (2042, 2012-06-28)
fpga_ver\db\alt_synch_pipe_9u7.tdf (2042, 2012-06-28)
fpga_ver\db\alt_synch_pipe_jcb.tdf (2156, 2012-06-29)
fpga_ver\db\alt_synch_pipe_kcb.tdf (2151, 2012-06-29)
fpga_ver\db\alt_synch_pipe_nc8.tdf (2094, 2012-06-29)
fpga_ver\db\alt_synch_pipe_oc8.tdf (2089, 2012-06-29)
fpga_ver\db\a_graycounter_62c.tdf (2786, 2012-06-28)
fpga_ver\db\a_graycounter_72c.tdf (3097, 2012-06-28)
fpga_ver\db\a_graycounter_8gc.tdf (2919, 2012-06-29)
fpga_ver\db\a_graycounter_9gc.tdf (3210, 2012-06-29)
fpga_ver\db\a_graycounter_i96.tdf (2785, 2012-06-28)
fpga_ver\db\cmpr_7dc.tdf (1593, 2012-06-28)
fpga_ver\db\cmpr_bdc.tdf (1915, 2012-06-28)
fpga_ver\db\cmpr_ddc.tdf (2074, 2012-06-28)
fpga_ver\db\cmpr_edc.tdf (2144, 2012-06-29)
fpga_ver\db\cmpr_v26.tdf (2205, 2012-06-28)
fpga_ver\db\cntr_06j.tdf (4846, 2012-06-28)
fpga_ver\db\cntr_4di.tdf (4753, 2012-06-28)
fpga_ver\db\cntr_5di.tdf (4753, 2012-06-29)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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