root_cordic
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：293KB
下载次数：26
上传日期：2013-10-12 17:40:24
上 传 者：
sml2010
说明： 这是求平方根的VHDL工程，使用CORDIC旋转坐标算法，完整的工程文档，可以仿真实验。
(This is the square root of the VHDL project using rotating coordinate CORDIC algorithm, a complete engineering documents, can be simulated experiments.)
文件列表:
root_cordic\ddddddddddd.v (1001, 2013-05-09)
root_cordic\ddddddddddd_v_beh.prj (104, 2013-05-09)
root_cordic\ddddddddddd_v_stx.prj (119, 2013-05-09)
root_cordic\isim\temp\hdllib.ref (249, 2013-05-09)
root_cordic\isim\temp\hdpdeps.ref (388, 2013-05-09)
root_cordic\isim\temp\vlg2D\glbl.bin (3405, 2013-05-09)
root_cordic\isim\temp\vlg6D\ddddddddddd__v.bin (1417, 2013-05-09)
root_cordic\isim\temp\vlg6F\top.bin (1360, 2013-05-09)
root_cordic\isim\work\ddddddddddd__v\ddddddddddd__v.h (969, 2013-05-09)
root_cordic\isim\work\ddddddddddd__v\mingw\ddddddddddd__v.obj (23456, 2013-05-09)
root_cordic\isim\work\glbl\glbl.h (946, 2013-05-08)
root_cordic\isim\work\glbl\mingw\glbl.obj (25164, 2013-05-08)
root_cordic\isim\work\hdllib.ref (333, 2013-05-09)
root_cordic\isim\work\hdpdeps.ref (500, 2013-05-09)
root_cordic\isim\work\top\mingw\top.obj (9747, 2013-05-08)
root_cordic\isim\work\top\top.h (893, 2013-05-08)
root_cordic\isim\work\vlg2D\glbl.bin (3405, 2013-05-08)
root_cordic\isim\work\vlg65\_t_e_s_t__v.bin (1404, 2013-05-08)
root_cordic\isim\work\vlg6D\ddddddddddd__v.bin (1417, 2013-05-09)
root_cordic\isim\work\vlg6F\top.bin (1360, 2013-05-08)
root_cordic\isim\work\_t_e_s_t__v\mingw\_t_e_s_t__v.obj (23172, 2013-05-08)
root_cordic\isim\work\_t_e_s_t__v\_t_e_s_t__v.h (954, 2013-05-08)
root_cordic\ROOT.asy (364, 2013-05-08)
root_cordic\ROOT.ngc (195632, 2013-05-08)
root_cordic\ROOT.sym (566, 2013-05-08)
root_cordic\ROOT.v (477657, 2013-05-08)
root_cordic\ROOT.veo (2990, 2013-05-08)
root_cordic\ROOT.vhd (4275, 2013-05-08)
root_cordic\ROOT.vho (3397, 2013-05-08)
root_cordic\ROOT.xco (1724, 2013-05-08)
root_cordic\root_cordic.ise (328201, 2013-05-09)
root_cordic\root_cordic.ise_ISE_Backup (328201, 2013-05-09)
root_cordic\ROOT_flist.txt (144, 2013-05-08)
root_cordic\ROOT_xmdf.tcl (2952, 2013-05-08)
root_cordic\ssssss.v (867, 2013-05-08)
root_cordic\ssssss_v_stx.prj (114, 2013-05-08)
root_cordic\templates\coregen.xml (1296, 2013-05-08)
root_cordic\TEST.v (991, 2013-05-08)
root_cordic\TEST_v_beh.prj (75, 2013-05-08)
... ...
The following files were generated for 'ROOT' in directory
C:\FPGAExercise\root_cordic:
ROOT.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
ROOT.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
ROOT.sym:
Please see the core data sheet.
ROOT.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
ROOT.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
ROOT.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
ROOT.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
ROOT.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
ROOT_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
ROOT_readme.txt:
Text file indicating the files generated and how they are used.
ROOT_xmdf.tcl:
Please see the core data sheet.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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