文件列表:

NAND_flash_verilog_vhdl (0, 2013-10-16)
NAND_flash_verilog_vhdl\doc (0, 2013-10-16)
NAND_flash_verilog_vhdl\doc\rd1055.pdf (628647, 2010-10-12)
NAND_flash_verilog_vhdl\project (0, 2013-10-16)
NAND_flash_verilog_vhdl\project\nand_flash_cntl.lpf (91, 2009-06-30)
NAND_flash_verilog_vhdl\project\nfcm_tb_vhd.udo_example (338, 2010-10-13)
NAND_flash_verilog_vhdl\simulation (0, 2013-10-16)
NAND_flash_verilog_vhdl\simulation\verilog (0, 2013-10-16)
NAND_flash_verilog_vhdl\simulation\verilog\rtl_verilog.do (101, 2010-10-13)
NAND_flash_verilog_vhdl\simulation\verilog\timing_verilog.do (228, 2010-10-13)
NAND_flash_verilog_vhdl\simulation\vhdl (0, 2013-10-16)
NAND_flash_verilog_vhdl\simulation\vhdl\rtl_vhdl.do (103, 2010-10-13)
NAND_flash_verilog_vhdl\simulation\vhdl\timing_vhdl.do (234, 2010-10-13)
NAND_flash_verilog_vhdl\source (0, 2013-10-16)
NAND_flash_verilog_vhdl\source\verilog (0, 2013-10-16)
NAND_flash_verilog_vhdl\source\verilog\ACounter.v (3023, 2010-01-19)
NAND_flash_verilog_vhdl\source\verilog\ErrLoc.v (2766, 2010-01-19)
NAND_flash_verilog_vhdl\source\verilog\H_gen.v (2863, 2010-01-19)
NAND_flash_verilog_vhdl\source\verilog\ipexpress (0, 2013-10-16)
NAND_flash_verilog_vhdl\source\verilog\ipexpress\xo (0, 2013-10-16)
NAND_flash_verilog_vhdl\source\verilog\ipexpress\xo2 (0, 2013-10-16)
NAND_flash_verilog_vhdl\source\verilog\ipexpress\xo2\ebr_buffer.lpc (797, 2010-10-12)
NAND_flash_verilog_vhdl\source\verilog\ipexpress\xo2\ebr_buffer.v (14227, 2010-10-12)
NAND_flash_verilog_vhdl\source\verilog\ipexpress\xo\ebr_buffer.lpc (891, 2009-05-08)
NAND_flash_verilog_vhdl\source\verilog\ipexpress\xo\ebr_buffer.v (8961, 2009-05-08)
NAND_flash_verilog_vhdl\source\verilog\ipexpress\xp2 (0, 2013-10-16)
NAND_flash_verilog_vhdl\source\verilog\ipexpress\xp2\ebr_buffer.lpc (892, 2009-10-28)
NAND_flash_verilog_vhdl\source\verilog\ipexpress\xp2\ebr_buffer.v (5134, 2009-10-28)
NAND_flash_verilog_vhdl\source\verilog\MFSM.v (20548, 2010-01-19)
NAND_flash_verilog_vhdl\source\verilog\nfcm_top.v (9454, 2010-01-19)
NAND_flash_verilog_vhdl\source\verilog\nfcm_top.vhd (13418, 2010-01-19)
NAND_flash_verilog_vhdl\source\verilog\TFSM.v (8246, 2010-01-19)
NAND_flash_verilog_vhdl\source\vhdl (0, 2013-10-16)
NAND_flash_verilog_vhdl\source\vhdl\ACounter.vhd (3113, 2010-01-19)
NAND_flash_verilog_vhdl\source\vhdl\ErrLoc.vhd (3284, 2010-01-19)
NAND_flash_verilog_vhdl\source\vhdl\H_gen.vhd (3278, 2010-01-19)
NAND_flash_verilog_vhdl\source\vhdl\ipexpress (0, 2013-10-16)
NAND_flash_verilog_vhdl\source\vhdl\ipexpress\xo (0, 2013-10-16)
NAND_flash_verilog_vhdl\source\vhdl\ipexpress\xo2 (0, 2013-10-16)
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NAND Flash Controller Reference Design =============================================================================== File List 1. RD1055/doc/rd1055.pdf --> NAND Flash Controller Reference Design document RD1055/doc/rd1055_readme.txt --> Read me file (this file) 2. RD1055/Project/nand_flash_cntl.lpf --> preference file for the design RD1055/Project/nfcm_tb_vhd.udo_example --> vital glitch removal example 3. /RD1055/simulation/verilog/rtl_verilog.do --> verilog rtl simulation script /RD1055/simulation/verilog/timing_verilog.do --> verilog timing simulation script /RD1055/simulation/vhdl/rtl_verilog.do --> vhdl rtl simulation script /RD1055/simulation/vhdl/timing_verilog.do --> vhdl timing simulation script 4. RD1055/source/verilog/ACounter.v --> source file RD1055/source/verilog/ErrLoc.v --> source file RD1055/source/verilog/MFSM.v --> source file RD1055/source/verilog/TFSM.v --> source file RD1055/source/verilog/H_gen.v --> source file RD1055/source/verilog/nfcm_top.v --> source file - top level RD1055/source/verilog/nfcm_top.vhd --> source file - vhdl wrapper RD1055/source/verilog/ipexpress/xo/ebr_buffer.v --> source file generated from IPexpress for xo device RD1055/source/verilog/ipexpress/xo/ebr_buffer.lpc --> configure file generated from IPexpress for xo device RD1055/source/verilog/ipexpress/xp2/ebr_buffer.v --> source file generated from IPexpress for xp2 device RD1055/source/verilog/ipexpress/xp2/ebr_buffer.lpc --> configure file generated from IPexpress for xp2 device RD1055/source/verilog/ipexpress/xo2/ebr_buffer.v --> source file generated from IPexpress for xo2 device RD1055/source/verilog/ipexpress/xo2/ebr_buffer.lpc --> configure file generated from IPexpress for xo2 device RD1055/source/vhdl/ACounter.vhd --> source file RD1055/source/vhdl/ErrLoc.vhd --> source file RD1055/source/vhdl/MFSM.vhd --> source file RD1055/source/vhdl/TFSM.vhd --> source file RD1055/source/vhdl/H_gen.vhd --> source file RD1055/source/vhdl/nfcm_top.vhd --> source file - vhdl wrapper RD1055/source/vhdl/ipexpress/xo/ebr_buffer.vhd --> source file generated from IPexpress for xo device RD1055/source/vhdl/ipexpress/xo/ebr_buffer.lpc --> configure file generated from IPexpress for xo device RD1055/source/vhdl/ipexpress/xp2/ebr_buffer.vhd --> source file generated from IPexpress for xp2 device RD1055/source/vhdl/ipexpress/xp2/ebr_buffer.lpc --> configure file generated from IPexpress for xp2 device RD1055/source/vhdl/ipexpress/xo2/ebr_buffer.vhd --> source file generated from IPexpress for xo2 device RD1055/source/vhdl/ipexpress/xo2/ebr_buffer.lpc --> configure file generated from IPexpress for xo2 device 5. RD1055/testbench/verilog/nfcm_tb.v --> top testbench for simulation RD1055/testbench/verilog/flash_interface.v --> flash interface source file for simulation RD1055/testbench/vhdl/nfcm_tb.vhd --> top testbench for simulation RD1055/testbench/vhdl/flash_interface.vhd --> flash interface source file for simulation =================================================================================================== !!IMPORTANT NOTES:!! 1. Unzip the RD1055_revyy.y.zip file using the existing folder names, where yy.y is the current version of the zip file 2. If there is lpf file or lci file available for the reference design: 2.1 copy the content of the provided lpf file to the .lpf file under your ispLEVER project, 2.2 use Constraint Files >> Add >> Exiting File to import the lpf to Diamond project and set it to be active, 2.3 copy the content of the provided lct file to the .lct under your cpld project. 4. If there is sty file (strategy file for Diamond) available for the design, go to File List tab on the left side of the GUI. Right click on Strategies >> Add >> Existing File. Then right click on the imported file name and select "Set as Active Strategy". =================================================================================================== Using ispLEVER or ispLEVER Classic software --------------------------------------------------------------------------------------------------- HOW TO CREATE A ISPLEVER OR ISPLEVER CLASSIC PROJECT: 1. Bring up ISPLEVER OR ISPLEVER CLASSIC software, in the GUI, select File >> New Project 2. In the New Project popup, select the Project location, provide a Project name, select Design Entry Type and click Next. 3. Use RD1055.pdf to see which device /speedgrade should be selected to achieve the desired timing result 4. Add the necessary source files from the RD1055\source directory, click Next 5. Click Finish. Now the project is successfully created. 6. Make sure the provided lpf or lct is used in the current directory. --------------------------------------------------------------------------------------------------- HOW TO RUN SIMULATION FROM ISPLEVER OR ISPLEVER CLASSIC PROJECT: 1. Import the top-level testbench into the project as test fixture and associate with the device 1.1 Import the rest as Testbench Dependency File by highligh and right click on the test bench file 2. In the Project Navigator, highlight the testbench file on the left-side panel, user will see 3 simulation options on the right panel. 3. For functional simulation, double click on Verilog (or VHDL) Functional Simulation with Aldec Active-HDL. Aldec simulator will be brought up, click yes to overwrite the existing file. The simulator will initialize and run for 1us. 4. Type "run 370us" for vhdl or "run -all" for verilog in the Console panel. A script similar to this will be in the Console panel: # KERNEL: 652ns: reset function # KERNEL: 696 nfcm_tb.reset_cycle << reset function over >> # KERNEL: 1052ns : auto block erase setup command # KERNEL: 1436ns : erase address:1234 # KERNEL: 1852ns : read status command # KERNEL: 2136 nfcm_tb.erase_cycle << erase no error >> # KERNEL: 2492ns : write page setup command # KERNEL: 166924ns : write page row address:1234 # KERNEL: 166924ns : random data write command # KERNEL: 168252ns : random write page column address:0835 # KERNEL: 168252ns : write page command # KERNEL: 168668ns : read status command # KERNEL: 168875 nfcm_tb.write_cycle << Writing no error >> # KERNEL: 169228ns : read page setup command # KERNEL: 16***36ns : read page row address:1234,column address:0000 # KERNEL: 16***36ns : read page command # KERNEL: 334108ns : random read page setup command # KERNEL: 334492ns : random read page column address:0835 # KERNEL: 334492ns : random read page command # KERNEL: 368440 nfcm_tb.read_cycle << ecc no error >> # KERNEL: 368796ns: read ID function # KERNEL: 369020ns : id code:69 # KERNEL: 369132ns : id code:ec # KERNEL: 369244ns : id code:f1 # KERNEL: 369356ns : id code:00 # KERNEL: 369448 nfcm_tb.read_id_cycle << read id function over >> vhdl user will see a script shown in the Console panel like this: run 370us # KERNEL: ***8 ns reset function # KERNEL: 696 ns << reset function over >> # KERNEL: 1048 ns reset function # KERNEL: 1432 ns auto block erase setup command # KERNEL: 1784 ns erase address: 0001001000110100 # KERNEL: 2072 ns << erase no error >> # KERNEL: 2424 ns read status command # KERNEL: 166856 ns write page setup command # KERNEL: 168184 ns write page row address: 0001001000110100 # KERNEL: 168184 ns random data write command # KERNEL: 168536 ns random write page column address: 0000100000110101 # KERNEL: 168536 ns write page command # KERNEL: 168747 ns << Writing no error >> # KERNEL: 169096 ns read status command # KERNEL: 169704 ns read page setup command # KERNEL: 333912 ns read page row address: 0001001000110100 # KERNEL: 333912 ns read page column address: 0000000000000000 # KERNEL: 333912 ns read page command # KERNEL: 334296 ns random read page setup command # KERNEL: 368248 ns << ecc no error >> # KERNEL: 368600 ns random read page column address: 0000100000110101 # KERNEL: 368600 ns random read page command # KERNEL: 368824 ns id code : 00000000 # KERNEL: 368936 ns id code : 11101100 # KERNEL: 369048 ns id code : 11110001 # KERNEL: 369160 ns id code : 00000000 # KERNEL: 369256 ns << read id function over >> # KERNEL: stopped at time: 370 us 5. For timing simulation, double click on Verilog (or VHDL) Post-Route Timing Simulation with Aldec Active-HDL. Similar message will be shown in the console panel of the Aldec Active-HDL simulator. 5.1 Run 370us to see the complete simulation 5.1 In timing simulation you may see some warnings about narrow widths or vital glitches. These warnings can be ignored. 5.2 Vital glitches can be removed by added a vsim command in the udo file. Use the udo.example under the \project directory =================================================================================================== Using Diamond Software --------------------------------------------------------------------------------------------------- HOW TO CREATE A PROJECT IN DIAMOND: 1. Launch Diamond software, in the GUI, select File >> New Project, click Next 2. In the New Project popup, select the Project location and provide a Project name and implementation name, click Next. 3. Add the necessary source files from the RD1055\source directory, click Next 4. Select the desired part and speedgrade. You may use RD1055.pdf to see which device and speedgrade can be selected to achieve the published timing result 5. Click Finish. Now the project is successfully created. 6. MAKE SURE the provided lpf and/or sty files are used in the current directory. ---------------------------------------------------------------------------------------------------- HOW TO RUN SIMULATION UNDER DIAMOND: 1. Bring up the Simulation Wizard under the Tools menu 2. Next provide a name for simulation project, and select RTL or post-route simulation 2.1 For post-route simulation, must export verilog or vhdl simulation file after Place and Route 3. Next add the test bench files form the RD1055\TestBench directory 3.1 For VHDL, make sure the top-level test bench is last to be added 4. Next click Finish, this will bring up the Aldec simulator automatically 5. In Aldec environment, you can manually activate the simulation or you can use a script 5.1 Use the provided script in the RD1055\Simulation\ directory a. For functional simulation, change the library name to the device family i) MachXO2: ovi_machxo2 for verilog, machxo2 for vhdl ii) MachXO: ovi_machxo for verilog, machxo for vhdl iii)XP2: ovi_xp2 for verilog, xp2 for vhdl b. For POST-ROUTE simulation, open the script and change the following: i) The *** file name and the path pointing to your *** file. The path usually looks like ".//<***_file_name>.***" ii) Change the library name using the library name described above c. Click Tools > Execute Macro and select the xxx.do file to run the simulation d. This will run the simulation until finish 5.2 Manually activate the simulation a. Click Simulation > Initialize Simulation b. Click File > New > Waveform, this will bring up the Waveform panel c. Click on the top-level testbench, drag all the signals into the Waveform panel d. At the Console panel, type "run 1500us" for VHDL simulation, or "run -all" for Verilog simulation e. For timing simulation, you must manually add -***max nfcm="./final_xo2/final_xo2_final_xo2_vo.***" into the asim or vsim command. Use the command in timing_xxx.do as an example 6. The simulation result will be similar to the one described in ispLEVER simulation section.

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